[PATCH v2 00/11] i.MX8M: speed up the PBL boot path (MMU, SHA-256, eMMC)

[Johannes Schneider]

This merges two v1 threads that review showed depend on the same first
step -- turning the MMU on in the PBL:

  - "crypto: sha256: PBL multi-block transform via ARMv8 Crypto
    Extensions" [1], where the ask was to keep the dispatch out of
    crypto/sha2.c [2]; and
  - "mci: imx-esdhc: speed up eMMC with ADMA2 + HS400 on i.MX8M" [3],
    where the ask was that PBL DMA needs the memory-synchronization
    (dma_map_*/dma_sync_*) the PBL lacks, and to concentrate on the MMU
    first since it is wanted anyway for a faster SHA-256 [4][5].

Ordered so it can be cut where it suits; each stage builds on the last:

  MMU
   1  enable the MMU + D-cache around the fw-external BL32 verify, via a
      new imx8m_mmu_early_enable() that derives the early-DRAM size from
      the DDR bus width [6]. ~720 KiB verify: ~2 s -> ~300 ms.

  SHA-256
   2  add the crypto-ext transform in a dedicated pbl/sha256.c, gated at
      runtime on ID_AA64ISAR0_EL1.SHA2 with a generic-C fallback.
      verify ~300 ms -> 3-5 ms.

  eMMC / PBL load
   3-7  barebox-proper eMMC speedups: SDHCI error-bail + i.MX ADMA2
        descriptor quirks, HS400/HS400ES, selectable transfer mode.
   8    enable the MMU before the PBL eMMC load so PIO runs warm-cached
        (load_bl33 713 ms -> 241 ms on i.MX8MM).
   *** DMA-free cut point. ***
   9-11 the PBL DMA path, now *with* the missing infrastructure: an opt-in
        CONFIG_PBL_HAS_DMA that gives the PBL real dma_map/dma_sync cache
        maintenance, SDHCI wired to it, and the i.MX8M PBL loader gaining
        SDMA/ADMA2 that select PBL_HAS_DMA and stay coherent with the
        D-cache on (load_bl33 241 ms -> 28 ms on i.MX8MM).

v1's "dma: make dma_mapping_error() NULL-safe" already landed in next and
is dropped. Based on next (261d2f8db0). Measured on i.MX8MM (GS05); both
the PIO+MMU and ADMA2 paths boot correctly (the BL32 SHA-256 verify
passing is the proof the PBL dma_sync is right).

[1] https://lists.infradead.org/pipermail/barebox/2026-June/056744.html
[2] https://lists.infradead.org/pipermail/barebox/2026-July/056890.html
[3] https://lists.infradead.org/pipermail/barebox/2026-June/056837.html
[4] https://lists.infradead.org/pipermail/barebox/2026-June/056842.html
[5] https://lists.infradead.org/pipermail/barebox/2026-July/056891.html
[6] https://lists.infradead.org/pipermail/barebox/2026-July/056889.html

Johannes Schneider (11):
  ARM: i.MX8M: enable MMU in PBL around fw-external BL32 verify
  crypto: sha256: PBL SHA-256 fast path via pbl/sha256.c
  mci: sdhci: bail out on ADMA/transfer errors instead of hanging
  mci: sdhci: honor BROKEN_ADMA_ZEROLEN_DESC / NO_ENDATTR_IN_NOPDESC
    quirks
  mci: imx-esdhc: mark the uSDHC ADMA2 descriptor quirks
  mci: imx-esdhc: support HS400 and HS400ES on i.MX8M
  mci: imx-esdhc: make the transfer mode selectable (PIO/SDMA/ADMA2)
  ARM: i.MX8M: enable the MMU before the PBL eMMC load
  dma: provide the streaming DMA API in the PBL (opt-in via PBL_HAS_DMA)
  mci: sdhci: honour dma_map/dma_sync in the PBL
  mci: imx-esdhc: DMA in the i.MX8M PBL eMMC loader

 arch/arm/cpu/Makefile          |  1 +
 arch/arm/crypto/Makefile       |  3 ++
 arch/arm/mach-imx/atf.c        | 30 +++++++++++
 common/Kconfig                 | 12 +++++
 crypto/Kconfig                 | 12 +++++
 drivers/dma/Makefile           |  1 +
 drivers/mci/Kconfig            | 46 ++++++++++++++--
 drivers/mci/imx-esdhc-common.c | 33 +++++++++---
 drivers/mci/imx-esdhc-pbl.c    | 91 ++++++++++++++++++++++++++++---
 drivers/mci/imx-esdhc.c        | 98 ++++++++++++++++++++++++++++++++--
 drivers/mci/imx-esdhc.h        | 14 +++++
 drivers/mci/sdhci.c            | 51 +++++++++++++-----
 drivers/mci/sdhci.h            |  4 ++
 include/crypto/pbl-sha.h       |  4 ++
 include/dma.h                  |  7 +--
 pbl/Makefile                   |  1 +
 pbl/decomp.c                   |  6 +--
 pbl/sha256.c                   | 85 +++++++++++++++++++++++++++++
 18 files changed, 459 insertions(+), 40 deletions(-)
 create mode 100644 pbl/sha256.c

-- 
2.43.0