[PATCH 05/19] riscv: implement elf_apply_relocations() for ELF relocation support
Sascha Hauer
s.hauer at pengutronix.de
Mon Jan 5 03:26:46 PST 2026
Add architecture-specific ELF relocation support for RISC-V,
enabling dynamic relocation of position-independent ELF binaries.
RISC-V implementation:
- Both RV32 and RV64 use RELA format with relocations:
* R_RISCV_NONE (0): No operation
* R_RISCV_32 (1): 32-bit absolute relocation (RV32)
* R_RISCV_64 (2): 64-bit absolute relocation (RV64)
* R_RISCV_RELATIVE (3): Base-relative adjustment
* Parse the PT_DYNAMIC section to find relocation tables
* Support both regular and PBL builds (obj-pbl-y)
* Follow the same pattern as ARM32/ARM64 implementations
* Validate ELF class matches architecture pointer size
* Return appropriate error codes for unsupported relocations
The relocation constants are added to arch/*/include/asm/elf.h for
use by the dynamic linker and bootloader code.
These implementations enable support for loading position-independent
ELF binaries in barebox PBL, which will be used when the compressed
payload is switched from raw binary to ELF format (similar to the
recent ARM changes).
🤖 Generated with [Claude Code](https://claude.com/claude-code)
Co-Authored-By: Claude Sonnet 4.5 <noreply at anthropic.com>
Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
arch/riscv/lib/Makefile | 1 +
arch/riscv/lib/elf_reloc.c | 212 +++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 213 insertions(+)
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 693248080070338ce26952cb1d9a831937d7f388..ee53e4602126d2ce7da2cdc42f21f92b22232f1a 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -3,6 +3,7 @@
extra-y += barebox.lds
obj-y += dtb.o
+obj-pbl-$(CONFIG_ELF) += elf_reloc.o
obj-pbl-y += sections.o setupc.o reloc.o sections.o runtime-offset.o
obj-$(CONFIG_ARCH_HAS_SJLJ) += setjmp.o longjmp.o
obj-$(CONFIG_RISCV_OPTIMZED_STRING_FUNCTIONS) += memcpy.o memset.o memmove.o
diff --git a/arch/riscv/lib/elf_reloc.c b/arch/riscv/lib/elf_reloc.c
new file mode 100644
index 0000000000000000000000000000000000000000..11e44e2c816185d7b4722f2ead698b32bd562de0
--- /dev/null
+++ b/arch/riscv/lib/elf_reloc.c
@@ -0,0 +1,212 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <common.h>
+#include <elf.h>
+#include <errno.h>
+#include <asm/elf.h>
+
+#if __SIZEOF_POINTER__ == 8
+
+/*
+ * Parse dynamic section and extract relocation info for RISC-V 64-bit
+ */
+static int parse_dynamic_section(struct elf_image *elf, Elf64_Dyn *dyn,
+ Elf64_Rela **rela_out, u64 *relasz_out)
+{
+ Elf64_Rela *rela = NULL;
+ u64 relasz = 0, relaent = 0;
+ int i;
+ phys_addr_t base = (phys_addr_t)elf->reloc_offset;
+
+ /* Iterate through dynamic entries until DT_NULL */
+ for (i = 0; dyn[i].d_tag != DT_NULL; i++) {
+ switch (dyn[i].d_tag) {
+ case DT_RELA:
+ /* RELA table address - needs to be adjusted by load offset */
+ rela = (Elf64_Rela *)(base + dyn[i].d_un.d_ptr);
+ break;
+ case DT_RELASZ:
+ relasz = dyn[i].d_un.d_val;
+ break;
+ case DT_RELAENT:
+ relaent = dyn[i].d_un.d_val;
+ break;
+ case DT_REL:
+ pr_err("RISC-V 64 uses RELA, not REL relocations\n");
+ return -EINVAL;
+ default:
+ break;
+ }
+ }
+
+ if (!rela || !relasz || relaent != sizeof(Elf64_Rela)) {
+ pr_debug("No relocations or invalid relocation info\n");
+ return -EINVAL;
+ }
+
+ *rela_out = rela;
+ *relasz_out = relasz;
+ return 0;
+}
+
+/*
+ * Apply RISC-V 64-bit ELF relocations
+ */
+int elf_apply_relocations(struct elf_image *elf, void *dyn_seg)
+{
+ Elf64_Dyn *dyn = dyn_seg;
+ Elf64_Rela *rela;
+ u64 relasz;
+ phys_addr_t base = (phys_addr_t)elf->reloc_offset;
+ int ret;
+
+ if (elf->class != ELFCLASS64) {
+ pr_err("Wrong ELF class for RISC-V 64 relocation\n");
+ return -EINVAL;
+ }
+
+ ret = parse_dynamic_section(elf, dyn, &rela, &relasz);
+ if (ret)
+ return ret;
+
+ /* Apply each relocation */
+ while (relasz > 0) {
+ u64 *fixup_addr;
+ u32 reloc_type = ELF64_R_TYPE(rela->r_info);
+
+ /* Calculate address to fix up */
+ fixup_addr = (u64 *)(base + rela->r_offset);
+
+ switch (reloc_type) {
+ case R_RISCV_NONE:
+ /* No operation */
+ break;
+
+ case R_RISCV_RELATIVE:
+ /* B(P) = B + A */
+ /* For RELA format: A = r_addend, B = base */
+ *fixup_addr = base + rela->r_addend;
+ break;
+
+ case R_RISCV_64:
+ /* B(P) = S + A */
+ /* S is the symbol value, for PIE it's base + addend */
+ *fixup_addr = base + rela->r_addend;
+ break;
+
+ default:
+ pr_err("Unsupported RISC-V relocation type: %u at offset 0x%llx\n",
+ reloc_type, rela->r_offset);
+ return -EINVAL;
+ }
+
+ rela++;
+ relasz -= sizeof(Elf64_Rela);
+ }
+
+ return 0;
+}
+
+#else /* 32-bit RISC-V */
+
+/*
+ * Parse dynamic section and extract relocation info for RISC-V 32-bit
+ */
+static int parse_dynamic_section(struct elf_image *elf, Elf32_Dyn *dyn,
+ Elf32_Rela **rela_out, u64 *relasz_out)
+{
+ Elf32_Rela *rela = NULL;
+ u64 relasz = 0, relaent = 0;
+ int i;
+ phys_addr_t base = (phys_addr_t)elf->reloc_offset;
+
+ /* Iterate through dynamic entries until DT_NULL */
+ for (i = 0; dyn[i].d_tag != DT_NULL; i++) {
+ switch (dyn[i].d_tag) {
+ case DT_RELA:
+ /* RELA table address - needs to be adjusted by load offset */
+ rela = (Elf32_Rela *)(base + dyn[i].d_un.d_ptr);
+ break;
+ case DT_RELASZ:
+ relasz = dyn[i].d_un.d_val;
+ break;
+ case DT_RELAENT:
+ relaent = dyn[i].d_un.d_val;
+ break;
+ case DT_REL:
+ pr_err("RISC-V 32 uses RELA, not REL relocations\n");
+ return -EINVAL;
+ default:
+ break;
+ }
+ }
+
+ if (!rela || !relasz || relaent != sizeof(Elf32_Rela)) {
+ pr_debug("No relocations or invalid relocation info\n");
+ return -EINVAL;
+ }
+
+ *rela_out = rela;
+ *relasz_out = relasz;
+ return 0;
+}
+
+/*
+ * Apply RISC-V 32-bit ELF relocations
+ */
+int elf_apply_relocations(struct elf_image *elf, void *dyn_seg)
+{
+ Elf32_Dyn *dyn = dyn_seg;
+ Elf32_Rela *rela;
+ u64 relasz;
+ phys_addr_t base = (phys_addr_t)elf->reloc_offset;
+ int ret;
+
+ if (elf->class != ELFCLASS32) {
+ pr_err("Wrong ELF class for RISC-V 32 relocation\n");
+ return -EINVAL;
+ }
+
+ ret = parse_dynamic_section(elf, dyn, &rela, &relasz);
+ if (ret)
+ return ret;
+
+ /* Apply each relocation */
+ while (relasz > 0) {
+ u32 *fixup_addr;
+ u32 reloc_type = ELF32_R_TYPE(rela->r_info);
+
+ /* Calculate address to fix up */
+ fixup_addr = (u32 *)(base + rela->r_offset);
+
+ switch (reloc_type) {
+ case R_RISCV_NONE:
+ /* No operation */
+ break;
+
+ case R_RISCV_RELATIVE:
+ /* B(P) = B + A */
+ /* For RELA format: A = r_addend, B = base */
+ *fixup_addr = base + rela->r_addend;
+ break;
+
+ case R_RISCV_32:
+ /* B(P) = S + A */
+ /* S is the symbol value, for PIE it's base + addend */
+ *fixup_addr = base + rela->r_addend;
+ break;
+
+ default:
+ pr_err("Unsupported RISC-V relocation type: %u at offset 0x%x\n",
+ reloc_type, rela->r_offset);
+ return -EINVAL;
+ }
+
+ rela++;
+ relasz -= sizeof(Elf32_Rela);
+ }
+
+ return 0;
+}
+
+#endif
--
2.47.3
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