Uart set up in PBL

[Ahmad Fatoum]

Hello Renaud,

On 05.03.21 14:08, Barbier, Renaud wrote:
>> So you load pbl/bare init barebox into SRAM, run PBIT memory test on DRAM,
>> then extract/copy barebox proper to DRAM or how does it work?
>>
> [Barbier, Renaud] 
> For now I have never used PBL on ARM (lwl-y => obj-y). Probably did not do right as I  tweaked the barebox linker script to have a TEXT_BASE. Only reason I did not use PBL is that it did not boot first few time I tried and the other way worked right away.
> 
> PBIT runs from SPI NOR flash which is not a problem as there is a DDR BIST unit on our ARM SOC. I did include the memtester from pyropus.ca too for a more comprehensive test and obviously it is very slow running from flash with D-cache off. An improvement would be to run from SRAM.
> 
> From the barebox_arm-reset_vector, the uart is set to a fixed baud rate, the DDR memory initialized and if PBIT is enabled a quick or comprehensive test is ran.  Otherwise use the BIST to initialise ECC if present and then barebox_arm_entry is called to relocate barebox in memory.

I see. I am afraid there's no suitable API for early variable
readout you can directly use. Some solutions that come to mind:

  - If you have early chainloading to copy the reset of barebox
    into DRAM, you could use it to load a data block with your own
    format

  - The sama5d2 boards use FAT from PBL, before barebox proper is
    initialized. Only if you have an early block driver.

  - Read it from i2c EEPROM if available: There is early i2c code
    for i.MX (used for SPD EEPROM)

  - Change memory test to log to memory and then write from barebox
    proper

  - Dedicate a word in barebox header for the baud rate and patch the binary
    in flash to override it...


I'd be interested in hearing what you eventually decide on.

Cheers,
Ahmad



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