[PATCH v2 07/29] RISC-V: socs: add Kconfig entry for StarFive JH7100

[Ahmad Fatoum]

The JH7100 is the StarFive SoC with SiFive CPUs in the pre-production
BeagleV. Th JH7110 in later boards will be cache-coherent, but the
JH7100 will need some workarounds.

Add Kconfig symbols, so newly introduced symbols can depend on them.

Signed-off-by: Ahmad Fatoum <a.fatoum at pengutronix.de>
---
 arch/riscv/Kconfig.socs | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index f1b431555fcd..8f955cd4d220 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -21,8 +21,12 @@ config SOC_VIRT
 	  Generates an image tht can be be booted by QEMU. The image is called
 	  barebox-dt-2nd.img
 
+config CPU_SIFIVE
+	bool
+
 config SOC_SIFIVE
 	bool "SiFive SoCs"
+	select CPU_SIFIVE
 	select RISCV_S_MODE
 	select CLK_SIFIVE
 	select CLK_SIFIVE_PRCI
@@ -41,4 +45,22 @@ config BOARD_HIFIVE
 
 endif
 
+config SOC_STARFIVE
+	bool "StarFive SoCs"
+	help
+	  This enables support for SiFive SoC platform hardware.
+
+if SOC_STARFIVE
+
+config SOC_STARFIVE_JH71XX
+	bool
+	select CPU_SIFIVE
+
+config SOC_STARFIVE_JH7100
+	bool
+	select SOC_STARFIVE_JH71XX
+
+endif
+
+
 endmenu
-- 
2.29.2