[PATCH] ARM: imx6: reset PLL2's PFD2 on i.MX6D

[Uwe Kleine-König]

The check for is_imx6q was introduced initially in

	f1f6d76370b3 ("ARM: i.MX6: correct work flow of PFDs from uboot-sources")

to differentiate between i.MX6DL+i.MX6SL and i.MX6Q. The i.MX6D must be
handled like the latter, so drop the check. i.MX6DL+i.MX6SL can be
ignored here since since

	a66596282413 ("imx6: lowlevel_init: Fix workaround for new i.MX6s chips")

the PFD handling is only done for i.MX6DQ.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-imx/imx6.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index ba8fb8964ac8..4391839a0b7e 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -77,7 +77,7 @@ void imx6_init_lowlevel(void)
 		       BM_ANADIG_PFD_480_PFD0_CLKGATE,
 		       MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_SET);
 		writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |
-		       (is_imx6q ? BM_ANADIG_PFD_528_PFD2_CLKGATE : 0) |
+		       BM_ANADIG_PFD_528_PFD2_CLKGATE |
 		       BM_ANADIG_PFD_528_PFD1_CLKGATE |
 		       BM_ANADIG_PFD_528_PFD0_CLKGATE,
 		       MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_SET);
@@ -88,7 +88,7 @@ void imx6_init_lowlevel(void)
 		       BM_ANADIG_PFD_480_PFD0_CLKGATE,
 		       MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_CLR);
 		writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |
-		       (is_imx6q ? BM_ANADIG_PFD_528_PFD2_CLKGATE : 0) |
+		       BM_ANADIG_PFD_528_PFD2_CLKGATE |
 		       BM_ANADIG_PFD_528_PFD1_CLKGATE |
 		       BM_ANADIG_PFD_528_PFD0_CLKGATE,
 		       MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_CLR);
-- 
2.8.1