[PATCH] mtd: nand-mxs: Gate ENFC_CLK_ROOT clock off before changing nand clock rate

[Sascha Hauer]

On Mon, Nov 17, 2014 at 12:58:34AM +0300, Dmitry Lavnikevich wrote:
> This fixes NAND initialization issue which appears occasionally on
> some i.MX6 SoCs (particulary was observed on phyCARD-i.MX6 with
> i.MX6Solo).
> 
> Signed-off-by: Dmitry Lavnikevich <d.lavnikevich at sam-solutions.com>

Applied, thanks

Sascha

> ---
>  arch/arm/mach-imx/include/mach/clock-imx6.h |  4 ++++
>  drivers/mtd/nand/nand_mxs.c                 | 12 ++++++++++++
>  2 files changed, 16 insertions(+)
> 
> diff --git a/arch/arm/mach-imx/include/mach/clock-imx6.h b/arch/arm/mach-imx/include/mach/clock-imx6.h
> index 8e5e9d9..ffa889d 100644
> --- a/arch/arm/mach-imx/include/mach/clock-imx6.h
> +++ b/arch/arm/mach-imx/include/mach/clock-imx6.h
> @@ -344,4 +344,8 @@
>  #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS			(1 << 2)
>  #define MXC_CCM_CGPR_PMIC_DELAY_SCALER			(1)
>  
> +/* Define the bits in register CCGR2 */
> +#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET		14
> +#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK		(3 << 14)
> +
>  #endif				/* __ARCH_ARM_MACH_MX6_CRM_REGS_H__ */
> diff --git a/drivers/mtd/nand/nand_mxs.c b/drivers/mtd/nand/nand_mxs.c
> index d5428bc..9ebddb3 100644
> --- a/drivers/mtd/nand/nand_mxs.c
> +++ b/drivers/mtd/nand/nand_mxs.c
> @@ -34,6 +34,8 @@
>  #include <stmp-device.h>
>  #include <asm/mmu.h>
>  #include <mach/generic.h>
> +#include <mach/clock-imx6.h>
> +#include <mach/imx6-regs.h>
>  
>  #define	MX28_BLOCK_SFTRST				(1 << 31)
>  #define	MX28_BLOCK_CLKGATE				(1 << 30)
> @@ -1254,6 +1256,7 @@ static int mxs_nand_probe(struct device_d *dev)
>  	struct nand_chip *nand;
>  	struct mtd_info *mtd;
>  	enum gpmi_type type;
> +	u32 val;
>  	int err;
>  
>  	err = dev_get_drvdata(dev, (unsigned long *)&type);
> @@ -1277,7 +1280,16 @@ static int mxs_nand_probe(struct device_d *dev)
>  		return PTR_ERR(nand_info->clk);
>  
>  	if (mxs_nand_is_imx6(nand_info)) {
> +		val = readl(MXC_CCM_CCGR2);
> +		val &= ~MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK;
> +		writel(val, MXC_CCM_CCGR2);
> +
>  		clk_set_rate(nand_info->clk, 96000000);
> +
> +		val = readl(MXC_CCM_CCGR2);
> +		val |= MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK;
> +		writel(val, MXC_CCM_CCGR2);
> +
>  		clk_enable(nand_info->clk);
>  		nand_info->dma_channel_base = 0;
>  	} else {
> -- 
> 2.1.3
> 
> 
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