Re: [RFC only] ARM: i.MX: Fix SDRAM size detect
shc_work at mail.ru
Fri Apr 26 07:50:55 EDT 2013
> > > On Fri, Apr 26, 2013 at 02:21:54PM +0400, Alexander Shiyan wrote:
> > > > This is a trying to fix problem described in:
> > > > http://lists.infradead.org/pipermail/barebox/2013-April/014182.html
> > >
> > > Sorry, can you explain what the problem is and how this patch fixes
> > > that?
> > > How I understood it the problem was that your board had the second chip
> > > select enabled without having sdram connected there leading to a wrong
> > > size detection.
> > ...
> > > > + arm_add_mem_device("ram0", MX51_CSD0_BASE_ADDR, size);
> > >
> > > With this patch you imply that imx_v3_sdram_size does not work which was
> > > never mentioned in the thread you reference.
> > >
> > > Can you please post:
> > >
> > > - Which values the sdram controller is programmed with
> > > - How much memory you really have
> > > - what barebox detects
> > Values for ESDCTL is programmed by DCD-data from flash_header.
> Yes, that happens on most i.MX using DCD data
> > Currently both channels are enabled and configured to 256M.
> > Barebox is NOT detect size of memory, it just a read back these values.
> > At least on every i.MX51 this is not works correctly. In any words:
> > How much we specify in flash_header, this is our "detected" size.
> > I have a two modules (256M and 512M),
> How is the layout? for 256M do you have a single chipselect with 256M or
> two chipselects with 128M each?
Single chipselect on 256M module. I.e. second is unused.
> Can you please post the output of:
> md 0x83fd9000+0x10
Values exactly same as in flash_header.
barebox at ConnectCore i.MX51:/ md 0x83fd9000+0x10
83fd9000: b2a20000 3f3584ab b2a20000 3f3584ab ......5?......5?
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