[PATCH 3/3] miidev: fix 1G wrong detection

[Johannes Stezenbach]

Hi,

On Fri, Sep 07, 2012 at 11:02:18AM +0200, Eric Bénard wrote:
> Le Fri, 7 Sep 2012 10:52:16 +0200,
> Johannes Stezenbach <js at sig21.net> a écrit :
> > On Thu, Sep 06, 2012 at 09:39:31PM +0200, Eric Bénard wrote:
> > > since 99e72c8bbdbdc690025a5868d831f1fe79ad56fc on an i.MX51 based board,
> > > I get : "phy0: Link is up - 1000/Full". It seems miidev tries to probe
> > > the PHY to early and gets 0x3ffff which leads to the wrong capabilities
> > > setting.
> > 
> > Hm, MII registers are only 16bit, why does your mii_read()
> > implementation return 0x3ffff?
> > 
> in fec_imx it returns the 32 bit register. I though we could mask it to
> only return the data but that wouldn't solve the problem as the tests
> in miidev would fail because the data is 0xFFFF.

Well, the check for the PHY ID registers was added for a purpose:
It allows barebox to print a useful error message if it can't talk
to the PHY, which is *much* better than letting you guess why
you ethernet doesn't work.  You could change the check to ">= 0xffff"
but it looks strange.  IMHO it would be better to mask the invalid
bits in your mii_read().

> > Also, what exactly do you mean by "too early"?  Your code
> > shouldn't call mii_register() before the MDIO clock is stable.
> > 
> fec_imx.c does that.

But why is it too early?  What do you need to wait for?
Maybe something in eth_device.open() enables MDIO?

Maybe it is actually better to defer PHY probing until
eth_device.open() is called, to save a few milliseconds during
boot from flash when ethernet isn't used.  But I have a board which can
have different PHY (e.g. 100Mbit or 1Gbit), and where one
of them doesn't answer to address 0, so I need to probe the address.
Then I would need to defer the mii_register() also
until eth_device.open()?


Thanks,
Johannes