[PATCH 3/5] ARM: ensure irqs are disabled at barebox exit

[Sascha Hauer]

On Sat, Oct 13, 2012 at 04:03:25PM +0200, Vicente wrote:
> 
> Signed-off-by: Vicente <vicencb at gmail.com>
> ---
>  arch/arm/cpu/cpu.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/arch/arm/cpu/cpu.c b/arch/arm/cpu/cpu.c
> index 51da3b5..2bfd3ed 100644
> --- a/arch/arm/cpu/cpu.c
> +++ b/arch/arm/cpu/cpu.c
> @@ -31,6 +31,7 @@
>  #include <asm/system_info.h>
>  #include <asm/cputype.h>
>  #include <asm/cache.h>
> +#include <asm/ptrace.h>
>  
>  /**
>   * Enable processor's instruction cache
> @@ -78,6 +79,16 @@ void arch_shutdown(void)
>  	mmu_disable();
>  #endif
>  	flush_icache();
> +	/*
> +	 * barebox normally does not use interrupts, but some functionalities
> +	 * (eg. OMAP4_USBBOOT) require them enabled. So be sure interrupts are
> +	 * disabled before exiting.
> +	 */
> +#if __LINUX_ARM_ARCH__ >= 6
> +	__asm__ __volatile__("cpsid i");
> +#else
> +	__asm__ __volatile__("msr cpsr_c, %0" : : "I"(PSR_I_BIT | SVC_MODE));
> +#endif

This won't work with multi ARM architecture support and also does not
compile in Thumb2 mode. So I suggest to do:

diff --git a/arch/arm/cpu/cpu.c b/arch/arm/cpu/cpu.c
index 25a0893..1328f0e 100644
--- a/arch/arm/cpu/cpu.c
+++ b/arch/arm/cpu/cpu.c
@@ -87,6 +87,23 @@ void arch_shutdown(void)
 		: "r0", "r1", "r2", "r3", "r6", "r10", "r12", "lr", "cc", "memory"
 	);
 #endif
+
+	/*
+	 * barebox normally does not use interrupts, but some functionalities
+	 * (eg. OMAP4_USBBOOT) require them enabled. So be sure interrupts are
+	 * disabled before exiting.
+	 */
+	if (cpu_architecture() >= CPU_ARCH_ARMv6) {
+#if __LINUX_ARM_ARCH__ >= 6
+		__asm__ __volatile__("cpsid i");
+#endif
+	} else {
+		uint32_t r;
+
+		__asm__ __volatile__("mrs %0, cpsr":"=r"(r));
+		r |= PSR_I_BIT;
+		__asm__ __volatile__("msr cpsr, %0" : : "r"(r));
+	}
 }
 
 #ifdef CONFIG_THUMB2_BAREBOX

Or the following which is simpler as it doesn't use the cpsid
instruction which is only available on >= ARMv6:


diff --git a/arch/arm/cpu/cpu.c b/arch/arm/cpu/cpu.c
index 25a0893..bfad49d 100644
--- a/arch/arm/cpu/cpu.c
+++ b/arch/arm/cpu/cpu.c
@@ -73,6 +73,8 @@ int icache_status(void)
  */
 void arch_shutdown(void)
 {
+	uint32_t r;
+
 #ifdef CONFIG_MMU
 	/* nearly the same as below, but this could also disable
 	 * second level cache.
@@ -87,6 +89,15 @@ void arch_shutdown(void)
 		: "r0", "r1", "r2", "r3", "r6", "r10", "r12", "lr", "cc", "memory"
 	);
 #endif
+
+	/*
+	 * barebox normally does not use interrupts, but some functionalities
+	 * (eg. OMAP4_USBBOOT) require them enabled. So be sure interrupts are
+	 * disabled before exiting.
+	 */
+	__asm__ __volatile__("mrs %0, cpsr":"=r"(r));
+	r |= PSR_I_BIT;
+	__asm__ __volatile__("msr cpsr, %0" : : "r"(r));
 }
 
 #ifdef CONFIG_THUMB2_BAREBOX

Sascha

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