[PATCH 7/8] nand_s3c2410: Fix sparse warnings.

[Marek Belisko]

warnings:
drivers/mtd/nand/nand_s3c2410.c:550:24: warning: cast adds address space to expression (<asn:2>)
drivers/mtd/nand/nand_s3c2410.c:561:10: warning: incorrect type in argument 1 (different base types)
drivers/mtd/nand/nand_s3c2410.c:594:4: warning: cast adds address space to expression (<asn:2>)
drivers/mtd/nand/nand_s3c2410.c:594:4: warning: cast adds address space to expression (<asn:2>)
drivers/mtd/nand/nand_s3c2410.c:623:26: warning: incorrect type in argument 1 (different address spaces)
drivers/mtd/nand/nand_s3c2410.c:623:26:    expected void [noderef] <asn:2>*host
drivers/mtd/nand/nand_s3c2410.c:623:26:    got void *<noident>

Signed-off-by: Marek Belisko <marek.belisko at open-nandra.com>
---
 drivers/mtd/nand/nand_s3c2410.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/nand/nand_s3c2410.c b/drivers/mtd/nand/nand_s3c2410.c
index c5f5d97..3a6f1e0 100644
--- a/drivers/mtd/nand/nand_s3c2410.c
+++ b/drivers/mtd/nand/nand_s3c2410.c
@@ -547,7 +547,7 @@ static void __nand_boot_init nfc_addr(void __iomem *host, uint32_t offs,
  */
 void __nand_boot_init s3c24x0_nand_load_image(void *dest, int size, int page)
 {
-	void __iomem *host = (void __iomem *)S3C24X0_NAND_BASE;
+	void __iomem *host = IOMEM(S3C24X0_NAND_BASE);
 	unsigned pagesize;
 	int i, cycle;
 
@@ -558,7 +558,7 @@ void __nand_boot_init s3c24x0_nand_load_image(void *dest, int size, int page)
 	enable_nand_controller(host, BOARD_DEFAULT_NAND_TIMING);
 
 	/* use the current NAND hardware configuration */
-	switch (readl(S3C24X0_NAND_BASE) & 0xf) {
+	switch (readl(host) & 0xf) {
 	case 0x6:	/* 8 bit, 4 addr cycles, 512 bpp, normal NAND */
 		pagesize = 512;
 		cycle = 4;
@@ -591,7 +591,7 @@ void __nand_boot_init s3c24x0_nand_load_image(void *dest, int size, int page)
 		wait_for_completion(host);
 		/* copy one page (do *not* use readsb() here!)*/
 		for (i = 0; i < pagesize; i++)
-			writeb(readb(host + NFDATA), (void __iomem *)(dest + i));
+			writeb(readb(IOMEM(host + NFDATA)), IOMEM(dest + i));
 		disable_cs(host);
 
 		page++;
@@ -620,7 +620,7 @@ static int do_nand_boot_test(struct command *cmdtp, int argc, char *argv[])
 	s3c24x0_nand_load_image(dest, size, 0);
 
 	/* re-enable the controller again, as this was a test only */
-	enable_nand_controller((void *)S3C24X0_NAND_BASE,
+	enable_nand_controller(IOMEM(S3C24X0_NAND_BASE),
 				BOARD_DEFAULT_NAND_TIMING);
 
 	return 0;
-- 
1.7.4.1