[PATCH 3/6] CPUIMX51: add ARM errata and enable L2 cache

[Sascha Hauer]

Hi Eric,

On Mon, Dec 12, 2011 at 10:19:36PM +0100, Eric Bénard wrote:
> - add ARM errata ID #468414
> - enable L2 cache to get better performances
> 
> Signed-off-by: Eric Bénard <eric at eukrea.com>
> ---
>  arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S |   10 ++++++++++
>  1 files changed, 10 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S b/arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S
> index 0b3726f..ee3b0fc 100644
> --- a/arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S
> +++ b/arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S

At the moment arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S and
./arch/arm/boards/freescale-mx51-pdk/lowlevel_init.S are exact copies.

What is being done first in board_init_lowlevel is

- workaround the errata
- configure aux control reg
- dis/enable L2 cache

This is basically the same as being done in mx53_init_lowlevel().
Can we instead add a mx5_init_lowlevel which contains the L2 cache
setting and is called from both mx51_init_lowlevel and mx53_lowlevel?

Sascha

> @@ -57,6 +57,11 @@
>  board_init_lowlevel:
>  	mov     r10, lr
>  
> +	/* ARM errata ID #468414 */
> +	mrc 15, 0, r1, c1, c0, 1
> +	orr r1, r1, #(1 << 5)    /* enable L1NEON bit */
> +	mcr 15, 0, r1, c1, c0, 1
> +
>  	/* explicitly disable L2 cache */
>  	mrc 15, 0, r0, c1, c0, 1
>  	bic r0, r0, #0x2
> @@ -76,6 +81,11 @@ board_init_lowlevel:
>  
>  	mcr 15, 1, r0, c9, c0, 2
>  
> +	/* enable L2 cache */
> +	mrc 15, 0, r0, c1, c0, 1
> +	orr r0, r0, #2
> +	mcr 15, 0, r0, c1, c0, 1
> +
>  	ldr r0, =MX51_CCM_BASE_ADDR
>  
>  	/* Gate of clocks to the peripherals first */
> -- 
> 1.7.6.4
> 
> 
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