[PATCH 3/6] omap3: Update method to detect si revision

[Sanjeev Premi]

This patch ensures that all silicon revisions
are detected. (Current implementation cannot
detect ES1.0).

In the process, the 'seemingly' hardcoded macros
identifying cpu revision (e.g. CPU_ES1P1) have
been updated to include the CPU name as well.
(The mapping of IDCODE value to silicon revision
may not be same across different OMAP families).

Signed-off-by: Sanjeev Premi <premi at ti.com>
---
 arch/arm/mach-omap/include/mach/sys_info.h |   21 ++++++---------
 arch/arm/mach-omap/omap3_generic.c         |   38 +++++++++++++++++++++++++---
 2 files changed, 42 insertions(+), 17 deletions(-)

diff --git a/arch/arm/mach-omap/include/mach/sys_info.h b/arch/arm/mach-omap/include/mach/sys_info.h
index f9df51c..8b8d332 100644
--- a/arch/arm/mach-omap/include/mach/sys_info.h
+++ b/arch/arm/mach-omap/include/mach/sys_info.h
@@ -51,20 +51,15 @@
 #define CPU_1610	0x1610
 
 /**
- * CPU revision
+ * Define CPU revisions
  */
-#define CPU_ES1		1
-#define CPU_ES1P1	2
-#define CPU_ES1P2	3
-#define CPU_ES2		4
-#define CPU_ES2P1	5
-#define CPU_ES2P2	6
-#define CPU_ES3		7
-#define CPU_ES3P1	8
-#define CPU_ES3P2	9
-#define CPU_ES4		10
-#define CPU_ES4P1	11
-#define CPU_ES4P2	12
+#define	cpu_revision(cpu,rev)	(((cpu) << 16) | (rev))
+
+#define OMAP34XX_ES1		cpu_revision(CPU_3430, 0)
+#define OMAP34XX_ES2		cpu_revision(CPU_3430, 1)
+#define OMAP34XX_ES2_1		cpu_revision(CPU_3430, 2)
+#define OMAP34XX_ES3		cpu_revision(CPU_3430, 3)
+#define OMAP34XX_ES3_1		cpu_revision(CPU_3430, 4)
 
 #define GPMC_MUXED		1
 #define GPMC_NONMUXED		0
diff --git a/arch/arm/mach-omap/omap3_generic.c b/arch/arm/mach-omap/omap3_generic.c
index cd9aceb..e146780 100644
--- a/arch/arm/mach-omap/omap3_generic.c
+++ b/arch/arm/mach-omap/omap3_generic.c
@@ -87,20 +87,50 @@ u32 get_cpu_type(void)
 }
 
 /**
- * @brief Extract the OMAP ES rev
+ * @brief Extract the OMAP ES revision
  *
- * @return CPU_ES version
+ * Latest known revision is considered default.
+ *
+ * @return silicon version
  */
 u32 get_cpu_rev(void)
 {
 	u32 idcode_val;
-	u32 version;
+	u32 version, retval;
 
 	idcode_val = readl(IDCODE_REG);
 
 	version = get_version(idcode_val);
 
-	return version;
+	/*
+	 * On OMAP3430 ES1.0 the IDCODE register is not exposed on L4.
+	 * Use CPU ID to check for the same.
+	 */
+	__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(retval));
+	if ((retval & 0xf) == 0x0) {
+		retval = OMAP34XX_ES1;
+	} else {
+		switch (version) {
+		case 0: /* This field was not set in early samples */
+		case 1:
+			retval = OMAP34XX_ES2;
+			break;
+		case 2:
+			retval = OMAP34XX_ES2_1;
+			break;
+		case 3:
+			retval = OMAP34XX_ES3;
+			break;
+		case 4:
+			/*
+			 * Same as default case
+			 */
+		default:
+			retval = OMAP34XX_ES3_1;
+		}
+	}
+
+	return retval;
 }
 
 /**
-- 
1.7.2.2