[PATCH 5/7] Enable TX done IRQs

[YanBo]

On Thu, May 30, 2013 at 4:17 PM, Pontus Fuchs <pontus.fuchs at gmail.com> wrote:
> On 2013-05-28 18:04, YanBo wrote:
>>
>> On Tue, May 28, 2013 at 10:59 PM, Pontus Fuchs <pontus.fuchs at gmail.com>
>> wrote:
>>>
>>> Generate a TX done IRQ when TX transfer is done.
>>>
>>> Signed-off-by: Pontus Fuchs <pontus.fuchs at gmail.com>
>>> ---
>>>   dxe.c | 44 +++++++++++++++++++++++++++++++++++---------
>>>   dxe.h |  4 ++--
>>>   2 files changed, 37 insertions(+), 11 deletions(-)
>>>
>>> diff --git a/dxe.h b/dxe.h
>>> index fa25ecc..62cefe9 100644
>>> --- a/dxe.h
>>> +++ b/dxe.h
>>> @@ -38,9 +38,9 @@ RX_HIGH       = DMA3
>>>   #define WCN36XX_DXE_CTRL_RX_L                  0x12ad2f
>>>   #define WCN36XX_DXE_CTRL_RX_H                  0x12d12f
>>>   #define WCN36XX_DXE_CTRL_TX_H_BD               0x32ce45
>>> -#define WCN36XX_DXE_CTRL_TX_H_SKB              0x32ce4d
>>> +#define WCN36XX_DXE_CTRL_TX_H_SKB              0x33ce4d
>>
>>
>> Why the value change from 0x33X to 0x32x? the bit16 is enable, which
>> means the "STOP"  bit is set,
>> and the DMA engine will disable the channel after finish processing
>> this descriptor.
>
>
> I double checked and bit 16 is intr.
>

The bit 17 is the intr, please refer
#define WLANDXE_DESC_CTRL_STOP           0x00010000
#define WLANDXE_DESC_CTRL_INT            0x00020000

So change value from 0x32ce4d to 0x33ce4d means  (0X32ce4d |
WLANDXE_DESC_CTRL_STOP)
CCIIW.

Thanks

BR /Yanbo

> //Pontus
>