[PATCH v2 8/9] Enable TX done IRQs

[Pontus Fuchs]

Generate a TX done IRQ when TX transfer is done.

Signed-off-by: Pontus Fuchs <pontus.fuchs at gmail.com>
---
 dxe.c | 33 ++++++++++++++++++++++++++++++++-
 dxe.h |  4 ++--
 2 files changed, 34 insertions(+), 3 deletions(-)

diff --git a/dxe.c b/dxe.c
index 046bea4..adcd700 100644
--- a/dxe.c
+++ b/dxe.c
@@ -273,6 +273,38 @@ static void wcn36xx_dxe_ch_free_skbs(struct wcn36xx *wcn,
 
 static irqreturn_t wcn36xx_irq_tx_complete(int irq, void *dev)
 {
+	struct wcn36xx *wcn = (struct wcn36xx *)dev;
+	int int_src, int_reason;
+
+	wcn36xx_dxe_read_register(wcn, WCN36XX_DXE_INT_SRC_RAW_REG, &int_src);
+
+	if (int_src & WCN36XX_INT_MASK_CHAN_TX_H) {
+		wcn36xx_dxe_read_register(wcn,
+					  WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_H,
+					  &int_reason);
+
+		wcn36xx_dxe_write_register(wcn,
+					   WCN36XX_DXE_0_INT_CLR,
+					   WCN36XX_INT_MASK_CHAN_TX_H);
+
+		wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_0_INT_ED_CLR,
+					   WCN36XX_INT_MASK_CHAN_TX_H);
+		wcn36xx_dbg(WCN36XX_DBG_DXE, "dxe tx ready high");
+	}
+	if (int_src & WCN36XX_INT_MASK_CHAN_TX_L) {
+		wcn36xx_dxe_read_register(wcn,
+					  WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_L,
+					  &int_reason);
+
+		wcn36xx_dxe_write_register(wcn,
+					   WCN36XX_DXE_0_INT_CLR,
+					   WCN36XX_INT_MASK_CHAN_TX_L);
+
+		wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_0_INT_ED_CLR,
+					   WCN36XX_INT_MASK_CHAN_TX_L);
+		wcn36xx_dbg(WCN36XX_DBG_DXE, "dxe tx ready low");
+	}
+
 	return IRQ_HANDLED;
 }
 
@@ -300,7 +332,6 @@ static int wcn36xx_dxe_request_irqs(struct wcn36xx *wcn)
 		wcn36xx_error("failed to alloc rx irq");
 		goto out_txirq;
 	}
-	disable_irq_nosync(wcn->tx_irq);
 	enable_irq_wake(wcn->rx_irq);
 	return 0;
 
diff --git a/dxe.h b/dxe.h
index b93f13a..61a46de 100644
--- a/dxe.h
+++ b/dxe.h
@@ -39,9 +39,9 @@ H2H_TEST_RX_TX = DMA2
 #define WCN36XX_DXE_CTRL_RX_L			0x12ad2f
 #define WCN36XX_DXE_CTRL_RX_H			0x12d12f
 #define WCN36XX_DXE_CTRL_TX_H_BD		0x32ce45
-#define WCN36XX_DXE_CTRL_TX_H_SKB		0x32ce4d
+#define WCN36XX_DXE_CTRL_TX_H_SKB		0x33ce4d
 #define WCN36XX_DXE_CTRL_TX_L_BD		0x328a45
-#define WCN36XX_DXE_CTRL_TX_L_SKB		0x328a4d
+#define WCN36XX_DXE_CTRL_TX_L_SKB		0x338a4d
 
 // TODO This must calculated properly but not hardcoded
 #define WCN36XX_DXE_WQ_TX_L			0x17
-- 
1.8.1.2