[PATCH v2 2/4] Simplify wcn36xx_dxe_desc structure
Pontus Fuchs
pontus.fuchs at gmail.com
Wed May 29 07:57:31 EDT 2013
No need to have the union or the embedded struct.
Signed-off-by: Pontus Fuchs <pontus.fuchs at gmail.com>
---
dxe.c | 56 ++++++++++++++++++++++++++++----------------------------
dxe.h | 59 ++++++++++++++++++++++++++++-------------------------------
2 files changed, 56 insertions(+), 59 deletions(-)
diff --git a/dxe.c b/dxe.c
index ec95d9f..225ad64 100644
--- a/dxe.c
+++ b/dxe.c
@@ -160,31 +160,31 @@ static int wcn36xx_dxe_init_descs(struct wcn36xx_dxe_ch *wcn_ch)
switch (wcn_ch->ch_type) {
case WCN36XX_DXE_CH_TX_L:
- cur_dxe_desc->desc_ctl.ctrl = WCN36XX_DXE_CTRL_TX_L;
- cur_dxe_desc->desc.dst_addr_l = WCN36XX_DXE_WQ_TX_L;
+ cur_dxe_desc->ctrl = WCN36XX_DXE_CTRL_TX_L;
+ cur_dxe_desc->dst_addr_l = WCN36XX_DXE_WQ_TX_L;
break;
case WCN36XX_DXE_CH_TX_H:
- cur_dxe_desc->desc_ctl.ctrl = WCN36XX_DXE_CTRL_TX_H;
- cur_dxe_desc->desc.dst_addr_l = WCN36XX_DXE_WQ_TX_H;
+ cur_dxe_desc->ctrl = WCN36XX_DXE_CTRL_TX_H;
+ cur_dxe_desc->dst_addr_l = WCN36XX_DXE_WQ_TX_H;
break;
case WCN36XX_DXE_CH_RX_L:
- cur_dxe_desc->desc_ctl.ctrl = WCN36XX_DXE_CTRL_RX_L;
- cur_dxe_desc->desc.src_addr_l = WCN36XX_DXE_WQ_RX_L;
+ cur_dxe_desc->ctrl = WCN36XX_DXE_CTRL_RX_L;
+ cur_dxe_desc->src_addr_l = WCN36XX_DXE_WQ_RX_L;
break;
case WCN36XX_DXE_CH_RX_H:
- cur_dxe_desc->desc_ctl.ctrl = WCN36XX_DXE_CTRL_RX_H;
- cur_dxe_desc->desc.src_addr_l = WCN36XX_DXE_WQ_RX_H;
+ cur_dxe_desc->ctrl = WCN36XX_DXE_CTRL_RX_H;
+ cur_dxe_desc->src_addr_l = WCN36XX_DXE_WQ_RX_H;
break;
}
if (0 == i) {
- cur_dxe_desc->desc.phy_next_l = 0;
+ cur_dxe_desc->phy_next_l = 0;
} else if ((0 < i) && (i < wcn_ch->desc_num - 1)) {
- prev_dxe_desc->desc.phy_next_l =
+ prev_dxe_desc->phy_next_l =
cur_dxe_ctl->desc_phy_addr;
} else if (i == (wcn_ch->desc_num -1)) {
- prev_dxe_desc->desc.phy_next_l =
+ prev_dxe_desc->phy_next_l =
cur_dxe_ctl->desc_phy_addr;
- cur_dxe_desc->desc.phy_next_l =
+ cur_dxe_desc->phy_next_l =
wcn_ch->head_blk_ctl->desc_phy_addr;
}
cur_dxe_ctl = cur_dxe_ctl->next;
@@ -214,10 +214,10 @@ static int wcn36xx_dxe_fill_skb(struct wcn36xx_dxe_ctl *cur_dxe_ctl)
skb = alloc_skb(WCN36XX_PKT_SIZE, GFP_ATOMIC);
if (skb == NULL)
return -ENOMEM;
- cur_dxe_desc->desc.dst_addr_l = dma_map_single(NULL,
- skb_tail_pointer(skb),
- WCN36XX_PKT_SIZE,
- DMA_FROM_DEVICE);
+ cur_dxe_desc->dst_addr_l = dma_map_single(NULL,
+ skb_tail_pointer(skb),
+ WCN36XX_PKT_SIZE,
+ DMA_FROM_DEVICE);
cur_dxe_ctl->skb = skb;
return 0;
}
@@ -300,17 +300,17 @@ int wcn36xx_rx_handle_packets(struct wcn36xx *wcn, struct wcn36xx_dxe_ch *ch)
dma_addr_t dma_addr;
struct sk_buff *skb;
- while (!(cur_dxe_desc->desc_ctl.ctrl & WCN36XX_DXE_CTRL_VALID_MASK)) {
+ while (!(cur_dxe_desc->ctrl & WCN36XX_DXE_CTRL_VALID_MASK)) {
skb = cur_dxe_ctl->skb;
- dma_addr = cur_dxe_desc->desc.dst_addr_l;
+ dma_addr = cur_dxe_desc->dst_addr_l;
wcn36xx_dxe_fill_skb(cur_dxe_ctl);
switch (ch->ch_type) {
case WCN36XX_DXE_CH_RX_L:
- cur_dxe_desc->desc_ctl.ctrl = WCN36XX_DXE_CTRL_RX_L;
+ cur_dxe_desc->ctrl = WCN36XX_DXE_CTRL_RX_L;
break;
case WCN36XX_DXE_CH_RX_H:
- cur_dxe_desc->desc_ctl.ctrl = WCN36XX_DXE_CTRL_RX_H;
+ cur_dxe_desc->ctrl = WCN36XX_DXE_CTRL_RX_H;
break;
default:
wcn36xx_warn("Unknow received channel");
@@ -445,11 +445,11 @@ int wcn36xx_dxe_tx(struct wcn36xx *wcn,
cur_dxe_ctl->frame = mem_pool->virt_addr;
// Set source address of the BD we send
- cur_dxe_desc->desc.src_addr_l = (int)mem_pool->phy_addr;
+ cur_dxe_desc->src_addr_l = (int)mem_pool->phy_addr;
- cur_dxe_desc->desc.dst_addr_l = cur_ch->dxe_wq;
+ cur_dxe_desc->dst_addr_l = cur_ch->dxe_wq;
cur_dxe_desc->fr_len = sizeof(struct wcn36xx_tx_bd);
- cur_dxe_desc->desc_ctl.ctrl = cur_ch->ctrl_bd;
+ cur_dxe_desc->ctrl = cur_ch->ctrl_bd;
wcn36xx_dbg(WCN36XX_DBG_DXE, "DXE TX");
@@ -463,16 +463,16 @@ int wcn36xx_dxe_tx(struct wcn36xx *wcn,
cur_dxe_ctl = (struct wcn36xx_dxe_ctl*)cur_dxe_ctl->next;
cur_dxe_ctl->skb = skb;
cur_dxe_desc = cur_dxe_ctl->desc;
- cur_dxe_desc->desc.src_addr_l = (int)dma_map_single(NULL,
+ cur_dxe_desc->src_addr_l = (int)dma_map_single(NULL,
cur_dxe_ctl->skb->data,
cur_dxe_ctl->skb->len,
DMA_TO_DEVICE );
- cur_dxe_desc->desc.dst_addr_l = cur_ch->dxe_wq;
+ cur_dxe_desc->dst_addr_l = cur_ch->dxe_wq;
cur_dxe_desc->fr_len = cur_dxe_ctl->skb->len;
// set it to VALID
- cur_dxe_desc->desc_ctl.ctrl = cur_ch->ctrl_skb;
+ cur_dxe_desc->ctrl = cur_ch->ctrl_skb;
wcn36xx_dbg_dump(WCN36XX_DBG_DXE_DUMP, "DESC2 >>> ",
(char*)cur_dxe_desc, sizeof(*cur_dxe_desc));
@@ -553,7 +553,7 @@ int wcn36xx_dxe_init(struct wcn36xx *wcn)
// Program preallocated destionatio Address
wcn36xx_dxe_write_register(wcn,
WCN36XX_DXE_CH_DEST_ADDR_RX_L,
- wcn->dxe_rx_l_ch.head_blk_ctl->desc->desc.phy_next_l);
+ wcn->dxe_rx_l_ch.head_blk_ctl->desc->phy_next_l);
// Enable default control registers
@@ -584,7 +584,7 @@ int wcn36xx_dxe_init(struct wcn36xx *wcn)
// Program preallocated destionatio Address
wcn36xx_dxe_write_register(wcn,
WCN36XX_DXE_CH_DEST_ADDR_RX_H,
- wcn->dxe_rx_h_ch.head_blk_ctl->desc->desc.phy_next_l);
+ wcn->dxe_rx_h_ch.head_blk_ctl->desc->phy_next_l);
// Enable default control registers
wcn36xx_dxe_write_register(wcn,
diff --git a/dxe.h b/dxe.h
index 86fceaa..31f9bab 100644
--- a/dxe.h
+++ b/dxe.h
@@ -169,40 +169,37 @@ struct wcn36xx_pkt {
void *int_data;
};
-// DXE descriptor data type
-struct wcn36xx_dxe_desc_data
-{
- int src_addr_l;
- int dst_addr_l;
- int phy_next_l;
- int src_addr_h;
- int dst_addr_h;
- int phy_next_h;
-};
-
struct wcn36xx_dxe_desc
{
- union
- {
- u32 ctrl;
- u32 valid :1; //0 = DMA stop, 1 = DMA continue with this descriptor
- u32 transfer_type :2; //0 = Host to Host space
- u32 eop :1; //End of Packet
- u32 bd_handling :1; //if transferType = Host to BMU, then 0 means first 128 bytes contain BD, and 1 means create new empty BD
- u32 siq :1; // SIQ
- u32 diq :1; // DIQ
- u32 pdu_rel :1; //0 = don't release BD and PDUs when done, 1 = release them
- u32 bthld_sel :4; //BMU Threshold Select
- u32 prio :3; //Specifies the priority level to use for the transfer
- u32 stop_channel :1; //1 = DMA stops processing further, channel requires re-enabling after this
- u32 intr :1; //Interrupt on Descriptor Done
- u32 rsvd :1; //reserved
- u32 size :14; //14 bits used - ignored for BMU transfers, only used for host to host transfers?
- } desc_ctl;
- int fr_len;
- struct wcn36xx_dxe_desc_data desc;
-};
+ u32 ctrl;
+/*
+ //TODO: Turn these into defines and start using them.
+ union {
+ u32 valid :1; //0 = DMA stop, 1 = DMA continue with this descriptor
+ u32 transfer_type :2; //0 = Host to Host space
+ u32 eop :1; //End of Packet
+ u32 bd_handling :1; //if transferType = Host to BMU, then 0 means first 128 bytes contain BD, and 1 means create new empty BD
+ u32 siq :1; // SIQ
+ u32 diq :1; // DIQ
+ u32 pdu_rel :1; //0 = don't release BD and PDUs when done, 1 = release them
+ u32 bthld_sel :4; //BMU Threshold Select
+ u32 prio :3; //Specifies the priority level to use for the transfer
+ u32 stop_channel :1; //1 = DMA stops processing further, channel requires re-enabling after this
+ u32 intr :1; //Interrupt on Descriptor Done
+ u32 rsvd :1; //reserved
+ u32 size :14; //14 bits used - ignored for BMU transfers, only used for host to host transfers?
+ } desc_ctl;
+*/
+ u32 fr_len;
+
+ u32 src_addr_l;
+ u32 dst_addr_l;
+ u32 phy_next_l;
+ u32 src_addr_h;
+ u32 dst_addr_h;
+ u32 phy_next_h;
+} __packed;
// DXE Control block
struct wcn36xx_dxe_ctl {
--
1.8.1.2
More information about the wcn36xx
mailing list