[PATCH 5/7] Enable TX done IRQs

[YanBo]

On Tue, May 28, 2013 at 10:59 PM, Pontus Fuchs <pontus.fuchs at gmail.com> wrote:
> Generate a TX done IRQ when TX transfer is done.
>
> Signed-off-by: Pontus Fuchs <pontus.fuchs at gmail.com>
> ---
>  dxe.c | 44 +++++++++++++++++++++++++++++++++++---------
>  dxe.h |  4 ++--
>  2 files changed, 37 insertions(+), 11 deletions(-)
>
> diff --git a/dxe.c b/dxe.c
> index adc8760..a4780fe 100644
> --- a/dxe.c
> +++ b/dxe.c
> @@ -264,6 +264,38 @@ static void wcn36xx_dxe_ch_free_skbs(struct wcn36xx *wcn,
>
>  static irqreturn_t wcn36xx_irq_tx_complete(int irq, void *dev)
>  {
> +       struct wcn36xx *wcn = (struct wcn36xx *)dev;
> +       int int_src, int_reason;
> +
> +       wcn36xx_dxe_read_register(wcn, WCN36XX_DXE_INT_SRC_RAW_REG, &int_src);
> +
> +       if (int_src & WCN36XX_INT_MASK_CHAN_TX_H) {
> +               wcn36xx_dxe_read_register(wcn,
> +                                         WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_H,
> +                                         &int_reason);
> +
> +               wcn36xx_dxe_write_register(wcn,
> +                                          WCN36XX_DXE_INT_CLR_ADDR,
> +                                          WCN36XX_INT_MASK_CHAN_TX_H);
> +
> +               wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_INT_END_CLR_ADDR,
> +                                          WCN36XX_INT_MASK_CHAN_TX_H);
> +               wcn36xx_dbg(WCN36XX_DBG_DXE, "dxe tx ready high");
> +       }
> +       if (int_src & WCN36XX_INT_MASK_CHAN_TX_L) {
> +               wcn36xx_dxe_read_register(wcn,
> +                                         WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_L,
> +                                         &int_reason);
> +
Here need some error judge about the interrupt reason, can be
implemented in another patch.
> +               wcn36xx_dxe_write_register(wcn,
> +                                          WCN36XX_DXE_INT_CLR_ADDR,
> +                                          WCN36XX_INT_MASK_CHAN_TX_L);
> +
> +               wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_INT_END_CLR_ADDR,
> +                                          WCN36XX_INT_MASK_CHAN_TX_L);
> +               wcn36xx_dbg(WCN36XX_DBG_DXE, "dxe tx ready low");
> +       }
> +

The TX packet will be freed when get the success TX packet, I guess
this will also be implemented in another patch?
>         return IRQ_HANDLED;

>  }
>
> @@ -278,25 +310,19 @@ static int wcn36xx_dxe_request_irqs(struct wcn36xx *wcn)
>  {
>         int ret;
>
> -       // Register TX complete irq
> -       ret =request_irq(wcn->tx_irq, wcn36xx_irq_tx_complete, IRQF_TRIGGER_HIGH,
> -                           "wcn36xx_tx", wcn);
> +       ret = request_irq(wcn->tx_irq, wcn36xx_irq_tx_complete,
> +                         IRQF_TRIGGER_HIGH, "wcn36xx_tx", wcn);
>         if (ret) {
>                 wcn36xx_error("failed to alloc tx irq");
>                 goto out_err;
>         }
>
> -       // Register RX irq
>         ret = request_irq(wcn->rx_irq, wcn36xx_irq_rx_ready, IRQF_TRIGGER_HIGH,
> -                           "wcn36xx_rx", wcn);
> +                         "wcn36xx_rx", wcn);
>         if (ret) {
>                 wcn36xx_error("failed to alloc rx irq");
>                 goto out_txirq;
>         }
> -       // disable tx irq, not supported
> -       disable_irq_nosync(wcn->tx_irq);
> -
> -       // enable rx irq
>         enable_irq_wake(wcn->rx_irq);
>         return 0;
>
> diff --git a/dxe.h b/dxe.h
> index fa25ecc..62cefe9 100644
> --- a/dxe.h
> +++ b/dxe.h
> @@ -38,9 +38,9 @@ RX_HIGH       = DMA3
>  #define WCN36XX_DXE_CTRL_RX_L                  0x12ad2f
>  #define WCN36XX_DXE_CTRL_RX_H                  0x12d12f
>  #define WCN36XX_DXE_CTRL_TX_H_BD               0x32ce45
> -#define WCN36XX_DXE_CTRL_TX_H_SKB              0x32ce4d
> +#define WCN36XX_DXE_CTRL_TX_H_SKB              0x33ce4d

Why the value change from 0x33X to 0x32x? the bit16 is enable, which
means the "STOP"  bit is set,
and the DMA engine will disable the channel after finish processing
this descriptor.

>  #define WCN36XX_DXE_CTRL_TX_L_BD               0x328a45
> -#define WCN36XX_DXE_CTRL_TX_L_SKB              0x328a4d
> +#define WCN36XX_DXE_CTRL_TX_L_SKB              0x338a4d
>
Same as above question

BR /Yanbo
>  // TODO This must calculated properly but not hardcoded
>  #define WCN36XX_DXE_WQ_TX_L                    0x17
> --
> 1.8.1.2
>
>
> _______________________________________________
> wcn36xx mailing list
> wcn36xx at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/wcn36xx