[PATCH 2/8] Style fixes for dxe.h
Pontus Fuchs
pontus.fuchs at gmail.com
Mon Jun 3 04:53:59 EDT 2013
Signed-off-by: Pontus Fuchs <pontus.fuchs at gmail.com>
---
dxe.h | 83 +++++++++++++++++++++++++++++++++----------------------------------
1 file changed, 41 insertions(+), 42 deletions(-)
diff --git a/dxe.h b/dxe.h
index 66f52c5..4eba4e7 100644
--- a/dxe.h
+++ b/dxe.h
@@ -26,14 +26,14 @@ RX_HIGH = DMA3
H2H_TEST_RX_TX = DMA2
*/
-// DXE registers
-#define WCN36XX_DXE_MEM_BASE 0x03000000
-#define WCN36XX_DXE_MEM_REG 0x202000
+/* DXE registers */
+#define WCN36XX_DXE_MEM_BASE 0x03000000
+#define WCN36XX_DXE_MEM_REG 0x202000
#define WCN36XX_DXE_CCU_INT 0xA0011
#define WCN36XX_DXE_REG_CCU_INT 0x200b10
-// TODO This must calculated properly but not hardcoded
+/* TODO This must calculated properly but not hardcoded */
#define WCN36XX_DXE_CTRL_TX_L 0x328a44
#define WCN36XX_DXE_CTRL_TX_H 0x32ce44
#define WCN36XX_DXE_CTRL_RX_L 0x12ad2f
@@ -43,7 +43,7 @@ H2H_TEST_RX_TX = DMA2
#define WCN36XX_DXE_CTRL_TX_L_BD 0x308a45
#define WCN36XX_DXE_CTRL_TX_L_SKB 0x328a4d
-// TODO This must calculated properly but not hardcoded
+/* TODO This must calculated properly but not hardcoded */
#define WCN36XX_DXE_WQ_TX_L 0x17
#define WCN36XX_DXE_WQ_TX_H 0x17
#define WCN36XX_DXE_WQ_RX_L 0xB
@@ -52,14 +52,14 @@ H2H_TEST_RX_TX = DMA2
/* DXE descriptor control filed */
#define WCN36XX_DXE_CTRL_VALID_MASK (0x00000001)
-// TODO This must calculated properly but not hardcoded
-// DXE default control register values
+/* TODO This must calculated properly but not hardcoded */
+/* DXE default control register values */
#define WCN36XX_DXE_CH_DEFAULT_CTL_RX_L 0x847EAD2F
#define WCN36XX_DXE_CH_DEFAULT_CTL_RX_H 0x84FED12F
#define WCN36XX_DXE_CH_DEFAULT_CTL_TX_H 0x853ECF4D
#define WCN36XX_DXE_CH_DEFAULT_CTL_TX_L 0x843e8b4d
-// Common DXE registers
+/* Common DXE registers */
#define WCN36XX_DXE_MEM_CSR (WCN36XX_DXE_MEM_REG + 0x00)
#define WCN36XX_DXE_REG_CSR_RESET (WCN36XX_DXE_MEM_REG + 0x00)
#define WCN36XX_DXE_ENCH_ADDR (WCN36XX_DXE_MEM_REG + 0x04)
@@ -88,48 +88,48 @@ H2H_TEST_RX_TX = DMA2
#define WCN36XX_DXE_REG_RESET 0x5c89
-// Temporary BMU Workqueue 4
+/* Temporary BMU Workqueue 4 */
#define WCN36XX_DXE_BMU_WQ_RX_LOW 0xB
#define WCN36XX_DXE_BMU_WQ_RX_HIGH 0x4
-// DMA channel offset
+/* DMA channel offset */
#define WCN36XX_DXE_TX_LOW_OFFSET 0x400
#define WCN36XX_DXE_TX_HIGH_OFFSET 0x500
#define WCN36XX_DXE_RX_LOW_OFFSET 0x440
#define WCN36XX_DXE_RX_HIGH_OFFSET 0x4C0
-// DXE Descriptor address where address of the next descriptor must be written
+/* Address of the next DXE descriptor */
#define WCN36XX_DXE_CH_NEXT_DESC_ADDR 0x001C
-#define WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_L WCN36XX_DXE_MEM_REG + WCN36XX_DXE_TX_LOW_OFFSET + WCN36XX_DXE_CH_NEXT_DESC_ADDR
-#define WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_H WCN36XX_DXE_MEM_REG + WCN36XX_DXE_TX_HIGH_OFFSET + WCN36XX_DXE_CH_NEXT_DESC_ADDR
-#define WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_L WCN36XX_DXE_MEM_REG + WCN36XX_DXE_RX_LOW_OFFSET + WCN36XX_DXE_CH_NEXT_DESC_ADDR
-#define WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_H WCN36XX_DXE_MEM_REG + WCN36XX_DXE_RX_HIGH_OFFSET + WCN36XX_DXE_CH_NEXT_DESC_ADDR
+#define WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_L (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_TX_LOW_OFFSET + WCN36XX_DXE_CH_NEXT_DESC_ADDR)
+#define WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_H (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_TX_HIGH_OFFSET + WCN36XX_DXE_CH_NEXT_DESC_ADDR)
+#define WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_L (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_RX_LOW_OFFSET + WCN36XX_DXE_CH_NEXT_DESC_ADDR)
+#define WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_H (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_RX_HIGH_OFFSET + WCN36XX_DXE_CH_NEXT_DESC_ADDR)
-// DXE Descriptor source address
+/* DXE Descriptor source address */
#define WCN36XX_DXE_CH_SRC_ADDR 0x000C
-#define WCN36XX_DXE_CH_SRC_ADDR_RX_L WCN36XX_DXE_MEM_REG + WCN36XX_DXE_RX_LOW_OFFSET + WCN36XX_DXE_CH_SRC_ADDR
-#define WCN36XX_DXE_CH_SRC_ADDR_RX_H WCN36XX_DXE_MEM_REG + WCN36XX_DXE_RX_HIGH_OFFSET + WCN36XX_DXE_CH_SRC_ADDR
+#define WCN36XX_DXE_CH_SRC_ADDR_RX_L (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_RX_LOW_OFFSET + WCN36XX_DXE_CH_SRC_ADDR)
+#define WCN36XX_DXE_CH_SRC_ADDR_RX_H (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_RX_HIGH_OFFSET + WCN36XX_DXE_CH_SRC_ADDR)
-// DXE Descriptor address where destination address must be written
+/* DXE Descriptor address destination address */
#define WCN36XX_DXE_CH_DEST_ADDR 0x0014
-#define WCN36XX_DXE_CH_DEST_ADDR_TX_L WCN36XX_DXE_MEM_REG + WCN36XX_DXE_TX_LOW_OFFSET + WCN36XX_DXE_CH_DEST_ADDR
-#define WCN36XX_DXE_CH_DEST_ADDR_TX_H WCN36XX_DXE_MEM_REG + WCN36XX_DXE_TX_HIGH_OFFSET + WCN36XX_DXE_CH_DEST_ADDR
-#define WCN36XX_DXE_CH_DEST_ADDR_RX_L WCN36XX_DXE_MEM_REG + WCN36XX_DXE_RX_LOW_OFFSET + WCN36XX_DXE_CH_DEST_ADDR
-#define WCN36XX_DXE_CH_DEST_ADDR_RX_H WCN36XX_DXE_MEM_REG + WCN36XX_DXE_RX_HIGH_OFFSET + WCN36XX_DXE_CH_DEST_ADDR
+#define WCN36XX_DXE_CH_DEST_ADDR_TX_L (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_TX_LOW_OFFSET + WCN36XX_DXE_CH_DEST_ADDR)
+#define WCN36XX_DXE_CH_DEST_ADDR_TX_H (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_TX_HIGH_OFFSET + WCN36XX_DXE_CH_DEST_ADDR)
+#define WCN36XX_DXE_CH_DEST_ADDR_RX_L (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_RX_LOW_OFFSET + WCN36XX_DXE_CH_DEST_ADDR)
+#define WCN36XX_DXE_CH_DEST_ADDR_RX_H (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_RX_HIGH_OFFSET + WCN36XX_DXE_CH_DEST_ADDR)
-// DXE Descriptor where status of the interrupt is located
+/* Interrupt status */
#define WCN36XX_DXE_CH_STATUS_REG_ADDR 0x0004
-#define WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_L WCN36XX_DXE_MEM_REG + WCN36XX_DXE_TX_LOW_OFFSET + WCN36XX_DXE_CH_STATUS_REG_ADDR
-#define WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_H WCN36XX_DXE_MEM_REG + WCN36XX_DXE_TX_HIGH_OFFSET + WCN36XX_DXE_CH_STATUS_REG_ADDR
-#define WCN36XX_DXE_CH_STATUS_REG_ADDR_RX_L WCN36XX_DXE_MEM_REG + WCN36XX_DXE_RX_LOW_OFFSET + WCN36XX_DXE_CH_STATUS_REG_ADDR
-#define WCN36XX_DXE_CH_STATUS_REG_ADDR_RX_H WCN36XX_DXE_MEM_REG + WCN36XX_DXE_RX_HIGH_OFFSET + WCN36XX_DXE_CH_STATUS_REG_ADDR
+#define WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_L (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_TX_LOW_OFFSET + WCN36XX_DXE_CH_STATUS_REG_ADDR)
+#define WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_H (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_TX_HIGH_OFFSET + WCN36XX_DXE_CH_STATUS_REG_ADDR)
+#define WCN36XX_DXE_CH_STATUS_REG_ADDR_RX_L (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_RX_LOW_OFFSET + WCN36XX_DXE_CH_STATUS_REG_ADDR)
+#define WCN36XX_DXE_CH_STATUS_REG_ADDR_RX_H (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_RX_HIGH_OFFSET + WCN36XX_DXE_CH_STATUS_REG_ADDR)
-// DXE default control register
-#define WCN36XX_DXE_REG_CTL_RX_L WCN36XX_DXE_MEM_REG + WCN36XX_DXE_RX_LOW_OFFSET
-#define WCN36XX_DXE_REG_CTL_RX_H WCN36XX_DXE_MEM_REG + WCN36XX_DXE_RX_HIGH_OFFSET
-#define WCN36XX_DXE_REG_CTL_TX_H WCN36XX_DXE_MEM_REG + WCN36XX_DXE_TX_HIGH_OFFSET
-#define WCN36XX_DXE_REG_CTL_TX_L WCN36XX_DXE_MEM_REG + WCN36XX_DXE_TX_LOW_OFFSET
+/* DXE default control register */
+#define WCN36XX_DXE_REG_CTL_RX_L (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_RX_LOW_OFFSET)
+#define WCN36XX_DXE_REG_CTL_RX_H (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_RX_HIGH_OFFSET)
+#define WCN36XX_DXE_REG_CTL_TX_H (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_TX_HIGH_OFFSET)
+#define WCN36XX_DXE_REG_CTL_TX_L (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_TX_LOW_OFFSET)
-#define WCN36XX_SMSM_WLAN_TX_ENABLE 0x00000400
+#define WCN36XX_SMSM_WLAN_TX_ENABLE 0x00000400
#define WCN36XX_SMSM_WLAN_TX_RINGS_EMPTY 0x00000200
@@ -139,7 +139,7 @@ H2H_TEST_RX_TX = DMA2
#define WCN36XX_INT_MASK_CHAN_RX_H 0x00000008
#define WCN36XX_INT_MASK_CHAN_TX_H 0x00000010
-#define WCN36XX_BD_CHUNK_SIZE 128
+#define WCN36XX_BD_CHUNK_SIZE 128
#define WCN36XX_PKT_SIZE 0xF20
enum wcn36xx_dxe_ch_type {
@@ -149,7 +149,7 @@ enum wcn36xx_dxe_ch_type {
WCN36XX_DXE_CH_RX_H
};
-// amount of descriptors per channel
+/* amount of descriptors per channel */
enum wcn36xx_dxe_ch_desc_num {
WCN36XX_DXE_CH_DESC_NUMB_TX_L = 128,
WCN36XX_DXE_CH_DESC_NUMB_TX_H = 10,
@@ -157,11 +157,10 @@ enum wcn36xx_dxe_ch_desc_num {
WCN36XX_DXE_CH_DESC_NUMB_RX_H = 40
};
-struct wcn36xx_dxe_desc
-{
+struct wcn36xx_dxe_desc {
u32 ctrl;
/*
- //TODO: Turn these into defines and start using them.
+ //TODO: Drop these, the hard coded values above and start using hal.h
union {
u32 valid :1; //0 = DMA stop, 1 = DMA continue with this descriptor
u32 transfer_type :2; //0 = Host to Host space
@@ -188,7 +187,7 @@ struct wcn36xx_dxe_desc
u32 phy_next_h;
} __packed;
-// DXE Control block
+/* DXE Control block */
struct wcn36xx_dxe_ctl {
struct wcn36xx_dxe_ctl *next;
struct wcn36xx_dxe_desc *desc;
@@ -204,11 +203,11 @@ struct wcn36xx_dxe_ch {
void *cpu_addr;
dma_addr_t dma_addr;
enum wcn36xx_dxe_ch_desc_num desc_num;
- // DXE control block ring
+ /* DXE control block ring */
struct wcn36xx_dxe_ctl *head_blk_ctl;
struct wcn36xx_dxe_ctl *tail_blk_ctl;
- // DXE channel specific configs
+ /* DXE channel specific configs */
u32 dxe_wq;
u32 ctrl_bd;
u32 ctrl_skb;
--
1.8.1.2
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