From dwmw2 at infradead.org  Wed Mar  3 13:57:01 2021
From: dwmw2 at infradead.org (David Woodhouse)
Date: Wed, 03 Mar 2021 13:57:01 +0000
Subject: test
Message-ID: <E1lHRzp-0051gn-PD@desiato.infradead.org>

test


From dwmw2 at infradead.org  Wed Mar  3 13:57:27 2021
From: dwmw2 at infradead.org (David Woodhouse)
Date: Wed, 03 Mar 2021 13:57:27 +0000
Subject: test
Message-ID: <E1lHS0F-0051hl-5F@desiato.infradead.org>

test


From dwmw at u3832b3a9db3152.ant.amazon.com  Fri Mar  5 12:55:21 2021
From: dwmw at u3832b3a9db3152.ant.amazon.com (David Woodhouse)
Date: Fri, 5 Mar 2021 12:55:21 +0000
Subject: test
Message-ID: <526cd37628a44ebead694bc1dabf8dcc@EX13MTAUWB001.ant.amazon.com>

test



Amazon Development Centre (London) Ltd. Registered in England and Wales with registration number 04543232 with its registered office at 1 Principal Place, Worship Street, London EC2A 2FA, United Kingdom.





From tinghan.shen at mediatek.com  Thu Mar 18 04:53:02 2021
From: tinghan.shen at mediatek.com (Tinghan Shen)
Date: Thu, 18 Mar 2021 12:53:02 +0800
Subject: [PATCH] clk: mediatek: Remove unused MT8192 mcupm clock
Message-ID: <20210318045302.25580-1-tinghan.shen@mediatek.com>

From: "TingHan Shen" <tinghan.shen at mediatek.com>

Remove unused MT8192 mcupm clock

Signed-off-by: TingHan Shen <tinghan.shen at mediatek.com>
---
This patch depends on series "Mediatek MT8192 clock support"[1].

[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=379955
---
 drivers/clk/mediatek/clk-mt8192.c | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c
index 673dc60182f5..80df1903bd58 100644
--- a/drivers/clk/mediatek/clk-mt8192.c
+++ b/drivers/clk/mediatek/clk-mt8192.c
@@ -649,12 +649,6 @@ static const char * const aes_msdcfde_parents[] = {
 	"univpll_d6"
 };
 
-static const char * const mcupm_parents[] = {
-	"clk26m",
-	"mainpll_d6_d4",
-	"mainpll_d6_d2"
-};
-
 static const char * const sflash_parents[] = {
 	"clk26m",
 	"mainpll_d7_d8",
@@ -856,8 +850,6 @@ static const struct mtk_mux top_mtk_muxes[] = {
 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE_SEL, "aes_msdcfde_sel",
 		aes_msdcfde_parents, 0x100, 0x104, 0x108, 24, 3, 31, 0x00c, 1),
 	/* CLK_CFG_16 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUPM_SEL, "mcupm_sel",
-		mcupm_parents, 0x110, 0x114, 0x118, 0, 2, 7, 0x00c, 2),
 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SFLASH_SEL, "sflash_sel",
 		sflash_parents, 0x110, 0x114, 0x118, 8, 2, 15, 0x00c, 3),
 };
@@ -983,7 +975,6 @@ static const struct mtk_gate infra_clks[] = {
 	GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scpsys", "scp_sel", 4),
 	GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", "axi_sel", 5),
 	GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6),
-	GATE_INFRA0(CLK_INFRA_MCUPM, "infra_mcupm", "mcupm_sel", 7),
 	GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 8),
 	GATE_INFRA0(CLK_INFRA_GCE2, "infra_gce2", "axi_sel", 9),
 	GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10),
-- 
2.18.0

From tinghan.shen at mediatek.com  Thu Mar 18 05:27:04 2021
From: tinghan.shen at mediatek.com (Tinghan Shen)
Date: Thu, 18 Mar 2021 13:27:04 +0800
Subject: [PATCH] clk: mediatek: Remove unused MT8192 mcupm clock
In-Reply-To: <20210318045302.25580-1-tinghan.shen@mediatek.com>
References: <20210318045302.25580-1-tinghan.shen@mediatek.com>
Message-ID: <20210318052704.28086-1-tinghan.shen@mediatek.com>

From: "TingHan Shen" <tinghan.shen at mediatek.com>

Remove unused MT8192 mcupm clock

Signed-off-by: TingHan Shen <tinghan.shen at mediatek.com>
---
This patch depends on series "Mediatek MT8192 clock support"[1].

[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=379955
---
 drivers/clk/mediatek/clk-mt8192.c | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c
index 673dc60182f5..80df1903bd58 100644
--- a/drivers/clk/mediatek/clk-mt8192.c
+++ b/drivers/clk/mediatek/clk-mt8192.c
@@ -649,12 +649,6 @@ static const char * const aes_msdcfde_parents[] = {
 	"univpll_d6"
 };
 
-static const char * const mcupm_parents[] = {
-	"clk26m",
-	"mainpll_d6_d4",
-	"mainpll_d6_d2"
-};
-
 static const char * const sflash_parents[] = {
 	"clk26m",
 	"mainpll_d7_d8",
@@ -856,8 +850,6 @@ static const struct mtk_mux top_mtk_muxes[] = {
 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE_SEL, "aes_msdcfde_sel",
 		aes_msdcfde_parents, 0x100, 0x104, 0x108, 24, 3, 31, 0x00c, 1),
 	/* CLK_CFG_16 */
-	MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUPM_SEL, "mcupm_sel",
-		mcupm_parents, 0x110, 0x114, 0x118, 0, 2, 7, 0x00c, 2),
 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SFLASH_SEL, "sflash_sel",
 		sflash_parents, 0x110, 0x114, 0x118, 8, 2, 15, 0x00c, 3),
 };
@@ -983,7 +975,6 @@ static const struct mtk_gate infra_clks[] = {
 	GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scpsys", "scp_sel", 4),
 	GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", "axi_sel", 5),
 	GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6),
-	GATE_INFRA0(CLK_INFRA_MCUPM, "infra_mcupm", "mcupm_sel", 7),
 	GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 8),
 	GATE_INFRA0(CLK_INFRA_GCE2, "infra_gce2", "axi_sel", 9),
 	GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10),
-- 
2.18.0

From tinghan.shen at mediatek.com  Thu Mar 18 05:40:02 2021
From: tinghan.shen at mediatek.com (Tinghan Shen)
Date: Thu, 18 Mar 2021 13:40:02 +0800
Subject: [PATCH] clk: mediatek: Remove unused MT8192 mcupm clock
In-Reply-To: <20210318045302.25580-1-tinghan.shen@mediatek.com>
References: <20210318045302.25580-1-tinghan.shen@mediatek.com>
Message-ID: <20210318054002.29138-1-tinghan.shen@mediatek.com>

From: "TingHan Shen" <tinghan.shen at mediatek.com>

> Remove unused MT8192 mcupm clock
> 
> Signed-off-by: TingHan Shen <tinghan.shen at mediatek.com>
> ---
> This patch depends on series "Mediatek MT8192 clock support"[1].

test reply
> 
> [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=379955
> ---
>  drivers/clk/mediatek/clk-mt8192.c | 9 ---------
>  1 file changed, 9 deletions(-)
> 
> diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c
> index 673dc60182f5..80df1903bd58 100644
> --- a/drivers/clk/mediatek/clk-mt8192.c
> +++ b/drivers/clk/mediatek/clk-mt8192.c
> @@ -649,12 +649,6 @@ static const char * const aes_msdcfde_parents[] = {
>  	"univpll_d6"
>  };
>  
> -static const char * const mcupm_parents[] = {
> -	"clk26m",
> -	"mainpll_d6_d4",
> -	"mainpll_d6_d2"
> -};
> -
>  static const char * const sflash_parents[] = {
>  	"clk26m",
>  	"mainpll_d7_d8",
> @@ -856,8 +850,6 @@ static const struct mtk_mux top_mtk_muxes[] = {
>  	MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE_SEL, "aes_msdcfde_sel",
>  		aes_msdcfde_parents, 0x100, 0x104, 0x108, 24, 3, 31, 0x00c, 1),
>  	/* CLK_CFG_16 */
> -	MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUPM_SEL, "mcupm_sel",
> -		mcupm_parents, 0x110, 0x114, 0x118, 0, 2, 7, 0x00c, 2),
>  	MUX_GATE_CLR_SET_UPD(CLK_TOP_SFLASH_SEL, "sflash_sel",
>  		sflash_parents, 0x110, 0x114, 0x118, 8, 2, 15, 0x00c, 3),
>  };
> @@ -983,7 +975,6 @@ static const struct mtk_gate infra_clks[] = {
>  	GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scpsys", "scp_sel", 4),
>  	GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", "axi_sel", 5),
>  	GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6),
> -	GATE_INFRA0(CLK_INFRA_MCUPM, "infra_mcupm", "mcupm_sel", 7),
>  	GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 8),
>  	GATE_INFRA0(CLK_INFRA_GCE2, "infra_gce2", "axi_sel", 9),
>  	GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10),
> -- 
> 2.18.0

From tinghan.shen at mediatek.com  Thu Mar 18 05:34:47 2021
From: tinghan.shen at mediatek.com (Tinghan Shen)
Date: Thu, 18 Mar 2021 13:34:47 +0800
Subject: [PATCH] clk: mediatek: Remove unused MT8192 mcupm clock
In-Reply-To: <20210318045302.25580-1-tinghan.shen@mediatek.com>
References: <20210318045302.25580-1-tinghan.shen@mediatek.com>
Message-ID: <20210318053447.28576-1-tinghan.shen@mediatek.com>

From: "TingHan Shen" <tinghan.shen at mediatek.com>

> Remove unused MT8192 mcupm clock
> 
> Signed-off-by: TingHan Shen <tinghan.shen at mediatek.com>
> ---
> This patch depends on series "Mediatek MT8192 clock support"[1].

test reply
> 
> [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=379955
> ---
>  drivers/clk/mediatek/clk-mt8192.c | 9 ---------
>  1 file changed, 9 deletions(-)
> 
> diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c
> index 673dc60182f5..80df1903bd58 100644
> --- a/drivers/clk/mediatek/clk-mt8192.c
> +++ b/drivers/clk/mediatek/clk-mt8192.c
> @@ -649,12 +649,6 @@ static const char * const aes_msdcfde_parents[] = {
>  	"univpll_d6"
>  };
>  
> -static const char * const mcupm_parents[] = {
> -	"clk26m",
> -	"mainpll_d6_d4",
> -	"mainpll_d6_d2"
> -};
> -
>  static const char * const sflash_parents[] = {
>  	"clk26m",
>  	"mainpll_d7_d8",
> @@ -856,8 +850,6 @@ static const struct mtk_mux top_mtk_muxes[] = {
>  	MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE_SEL, "aes_msdcfde_sel",
>  		aes_msdcfde_parents, 0x100, 0x104, 0x108, 24, 3, 31, 0x00c, 1),
>  	/* CLK_CFG_16 */
> -	MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUPM_SEL, "mcupm_sel",
> -		mcupm_parents, 0x110, 0x114, 0x118, 0, 2, 7, 0x00c, 2),
>  	MUX_GATE_CLR_SET_UPD(CLK_TOP_SFLASH_SEL, "sflash_sel",
>  		sflash_parents, 0x110, 0x114, 0x118, 8, 2, 15, 0x00c, 3),
>  };
> @@ -983,7 +975,6 @@ static const struct mtk_gate infra_clks[] = {
>  	GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scpsys", "scp_sel", 4),
>  	GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", "axi_sel", 5),
>  	GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6),
> -	GATE_INFRA0(CLK_INFRA_MCUPM, "infra_mcupm", "mcupm_sel", 7),
>  	GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 8),
>  	GATE_INFRA0(CLK_INFRA_GCE2, "infra_gce2", "axi_sel", 9),
>  	GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10),
> -- 
> 2.18.0

