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Message-ID: &lt;20200212000444.Horde.lKaETCidKpI1mec-f8m0O4d@www.vdorst.com&gt;
From: =?utf-8?b?UmVuw6k=?= van Dorst &lt;opensource@vdorst.com&gt;
To: Petr =?utf-8?b?xaB0ZXRpYXI=?= &lt;ynezz@true.cz&gt;
Cc: openwrt-devel@lists.openwrt.org, Kristian Evensen
 &lt;kristian.evensen@gmail.com&gt;
Subject: Re: [OpenWrt-Devel] [PATCH] ramips: gsw_mt7621: disable PORT 5 MAC
 RX/TX flow control by default
References: &lt;47e09723-651a-abc6-2c2f-9552c3944e3c@nbd.name&gt;
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Quoting René van Dorst &lt;opensource@vdorst.com&gt;:

&gt; Quoting Petr Štetiar &lt;ynezz@true.cz&gt;:
&gt;
&gt;&gt; René van Dorst via openwrt-devel &lt;openwrt-devel@lists.openwrt.org&gt;  
&gt;&gt; [2020-02-11 15:59:52]:
&gt;&gt;
&gt;&gt; [adding Kristian to the Cc: loop]
&gt;&gt;
&gt;&gt;&gt;&gt; Looking at the current upstream driver implementation, it seems like the
&gt;&gt;&gt;&gt; TX/RX flow control is enabled only if the flow control pause option is
&gt;&gt;&gt;&gt; resolved from the device/link partner advertisements (or otherwise set).
&gt;&gt;&gt;&gt;
&gt;&gt;&gt;
&gt;&gt;&gt; With upstream you mean mainline 5.5 kernel?
&gt;&gt;
&gt;&gt; Yes, 5.6-rc1
&gt;&gt;
&gt;&gt;&gt; In the DTS the CPU port is defined as a fixed-link with pause enabled.
&gt;&gt;&gt; So the pause bits are always resolved/set.
&gt;&gt;
&gt;&gt; I see[1] port@6 with fixed-link, without pause property.
&gt;
&gt; Here is more information I wrote [1] about the mt7530 switch and it  
&gt; modes and also
&gt; the mt7621 example below. I used the pause because AFAIK there  
&gt; was/is no pause issue.
&gt;
&gt;&gt;
&gt;&gt;&gt; The hardware can't send the frames fast enough because of the PAUSE frames,
&gt;&gt;&gt; maybe to a slower device? The CPU is filling the tx ring faster then the
&gt;&gt;&gt; hardware sending it and eventually CPU overtakes the DMA head.  
&gt;&gt;&gt; Which causes an
&gt;&gt;&gt; issue/race/deadlock.
&gt;&gt;
&gt;&gt; Probably, I didn't tried to reproduce it or planning to do so.
&gt;&gt;
&gt;
&gt; I hope to reproduce it quick by reducing the TX ring size from 4096 to 256.
&gt;

Hi Petr,

I thing I looking in the right direction.
With this patch, reducing the tx_ring size to 4 * 4 = 16 packets, I can easily
trigger a transmit timeout.
Just create some traffic.


rene@pc-rene:~/dev/openwrt$ git diff
diff --git  
a/target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/mtk_eth_soc.c  
b/target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index c6f4d90193b3..09d5e75ec0b0 100644
---  
a/target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++  
b/target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -1658,7 +1658,7 @@ static int fe_probe(struct platform_device *pdev)
         priv-&gt;msg_enable = netif_msg_init(fe_msg_level,  
FE_DEFAULT_MSG_ENABLE);
         priv-&gt;rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
         priv-&gt;rx_ring.rx_buf_size = fe_max_buf_size(priv-&gt;rx_ring.frag_size);
-       priv-&gt;tx_ring.tx_ring_size = NUM_DMA_DESC;
+       priv-&gt;tx_ring.tx_ring_size = 4;
         priv-&gt;rx_ring.rx_ring_size = NUM_DMA_DESC;
         INIT_WORK(&amp;priv-&gt;pending_work, fe_pending_work);
         u64_stats_init(&amp;priv-&gt;hw_stats-&gt;syncp);

Greats,

René

&gt;&gt;&gt;&gt; Disabling the flow control on PORT 5 MAC seems to fix this issues as the
&gt;&gt;&gt;&gt; pause frames are then filtered out. While at it, I'm removing the if
&gt;&gt;&gt;&gt; condition completely as suggested, since this code is run only on mt7621
&gt;&gt;&gt;&gt; SoC, so there is no need to check for the silicon revisions.
&gt;&gt;&gt;&gt;
&gt;&gt;&gt;
&gt;&gt;&gt; Port 6 is connected to the first GMAC of the SOC, not port 5.
&gt;&gt;&gt; So it should be PORT 6 in your description also
&gt;&gt;
&gt;&gt; Ok, I took that &quot;PMCR_P5/PORT 5 MAC Control Register&quot; from
&gt;&gt; MT7621_ProgrammingGuide_GSW_v01.pdf. Couldnt find anything about P6, it's
&gt;&gt; quite confusing.
&gt;
&gt; I totally understand that. Lack of complete documentation is an issue.
&gt;
&gt; P6 = MAC6 in the documentation. AFAIK all the MACs do have the same register
&gt; layout. So MAC6 = PORT 6 and is connected to the first GMAC of the SOC.
&gt; PORT 5 = MAC5 and can be used as 2nd CPU port or connect to an external phy.
&gt; So MAC5, 2nd GMAC of the SOC and an external PHY share the same RGMII bus.
&gt; Depending on GPIO/PORT settings they are connected to the BUS. See  
&gt; also mt7530.txt
&gt; kernel doc for more info.
&gt;
&gt;&gt;
&gt;&gt; 1.  
&gt;&gt; https://elixir.bootlin.com/linux/v5.6-rc1/source/drivers/staging/mt7621-dts/mt7621.dtsi#L489
&gt;&gt;
&gt;&gt; -- ynezz
&gt;&gt;
&gt;&gt; _______________________________________________
&gt;&gt; openwrt-devel mailing list
&gt;&gt; openwrt-devel@lists.openwrt.org
&gt;&gt; https://lists.openwrt.org/mailman/listinfo/openwrt-devel
&gt;
&gt; [1]:  
&gt; https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/net/dsa/mt7530.txt#L38
&gt;
&gt; Greats,
&gt;
&gt; René




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