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From: Martin Blumenstingl &lt;martin.blumenstingl@googlemail.com&gt;
Date: Sun, 10 Jun 2018 15:23:18 +0200
Message-ID: &lt;CAFBinCAsSd8dNhfKO+ggNV0Ko3oXFCGTYp7-gM59M=qwTarkjA@mail.gmail.com&gt;
Subject: Re: [OpenWrt-Devel] [PATCH 2/3] mvebu: reduce speed to gen1 for
 armada 37xx devices pcie
To: tmn505@gmail.com
Cc: tomek_n@o2.pl, openwrt-devel@lists.openwrt.org
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On Sat, Jun 9, 2018 at 11:09 PM Tomasz Maciej Nowak &lt;tmn505@gmail.com&gt; wrot=
e:
&gt;
&gt; W dniu 09.06.2018 o 19:02, Martin Blumenstingl pisze:
&gt; &gt; On Sat, Jun 9, 2018 at 4:15 PM Tomasz Maciej Nowak &lt;tomek_n@o2.pl&gt; wrot=
e:
&gt; &gt;&gt;
&gt; &gt;&gt; Since the beginning there's been an issue with initializing the Athero=
s
&gt; &gt;&gt; based MiniPCIe wlan cards. Here's an example of kerenel log:
&gt; &gt;&gt;
&gt; &gt;&gt; advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x3c
&gt; &gt;&gt; advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x44
&gt; &gt;&gt; advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x4
&gt; &gt;&gt; ath9k 0000:00:00.0: enabling device (0000 -&gt; 0002)
&gt; &gt;&gt; advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x3c
&gt; &gt;&gt; advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0xc
&gt; &gt;&gt; advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x4
&gt; &gt;&gt; advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x40
&gt; &gt;&gt; ath9k 0000:00:00.0: request_irq failed
&gt; &gt;&gt; advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x4
&gt; &gt;&gt; ath9k: probe of 0000:00:00.0 failed with error -22
&gt; &gt;&gt;
&gt; &gt;&gt; The same happens for ath5k cards, while ath10k card didn't appear at
&gt; &gt;&gt; all (not detected). Following the issue on esppressobin.net forum [1]
&gt; &gt;&gt; the workaround seems to be limiting the speed of PCIe bridge to 1st
&gt; &gt;&gt; generation. This fixed the initialization of ath5k, ath9k and ath10k
&gt; &gt;&gt; cards. The change shouldn't affect the performance for wireless cards,
&gt; &gt;&gt; it could reduce the performance of storage controller cards but since
&gt; &gt;&gt; OpenWrt focuses on wireless connectivity, fixing compatibility with
&gt; &gt;&gt; wireless cards should be a priority.
&gt; &gt;&gt; For the record, the iwlwifi and mt76 cards were not affected by this
&gt; &gt;&gt; issue.
&gt; &gt; does this meant that the PCIe link speed depends on the board?
&gt;
&gt; No, that depends on the SoC board has and PCIe card which negotiates the =
speed and capabilities. It shouldn't depend on the board, of course if ther=
e are no design faults. Maybe some code in Atheros drivers also affects thi=
s or there's bug in aardvark enumerating code. The assessment of this is ou=
tside of my skills.
I was curious because officially the SoCs from the Armada 3700 series
support PCIe 2.0, so it seems strange to force/limit the hardware to
PCIe 1.0

&gt; &gt;
&gt; &gt; the PCI dt-bindings already specify a &quot;max-link-speed&quot; property, see [0=
]
&gt; &gt; there's even a helper function to parse that property: of_pci_get_max_l=
ink_speed
&gt; &gt;
&gt; &gt; this would give you control over the PCIe link speed per board (I am
&gt; &gt; assuming that the mvebu target uses devicetree).
&gt;
&gt; I tried this before submitting the patch, just to be sure retried it afte=
r Your mail. Setting this had no effect, the state was as if there was no c=
hange.
as far as I can see the pci-aardvark driver does not parse the
&quot;max-link-speed&quot; devicetree property yet (because it does not use/call
of_pci_get_max_link_speed).
so to use the &quot;max-link-speed&quot; property one would:
- implement support for it in the driver
- add the property to the .dts file

&gt; &gt; additionally this would allow you to send the patch upstream so
&gt; &gt; OpenWrt doesn't have to carry custom patches around forever
&gt; &gt;
&gt; &gt; what do you think?
&gt;
&gt; This driver still is in early stage, there are still some issues, until i=
t'll be more mature I'm reluctant to send this workaround upstream or sendi=
ng bug report. Thomas Petazzoni from Bootlin is working on this driver and =
still has some pending changes but that will take few months. Until his cha=
nges will hit upstream I'm inclined to keep this.
I'm not against adding this patch
it just seems to me that all PCI related kernel patches in OpenWrt are
backports from upstream patches
so why not report your issue upstream, work on a fix with them and
backport the result (this will make kernel updates on the mvebu target
easier, since it'll allow dropping patches when updating rather then
having to figure out why they are still needed, rebasing and testing
them again, ...)

&gt; There is also upcoming device from CZ.nic, namely Turris MOX, which is ba=
sed on the same processor as ESPRESSObin. They already submitted watchdog d=
river to LKML and U-Boot tree and minor fixes to U-Boot. Maybe their involv=
ement will speed up the changes and we'll see this workaround unnecessary.
by sending your patch (even if you think that it's not in shape to be
applied upstream - then just state that explicitly) upstream you may
save other developers lots of time since you already found a way to
make some Atheros PCIe devices work with this controller/driver :)


Regards
Martin

]