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Tue, 29 May 2018 18:57:42 +0000 From: Kevin Darbyshire-Bryant <kevin@darbyshire-bryant.me.uk> To: Linus Walleij <linus.walleij@linaro.org> CC: Andrew Lunn <andrew@lunn.ch>, netdev <netdev@vger.kernel.org>, Florian Fainelli <f.fainelli@gmail.com>, LEDE Development List <openwrt-devel@lists.openwrt.org>, Vivien Didelot <vivien.didelot@savoirfairelinux.com> Subject: Re: [OpenWrt-Devel] [PATCH 0/4 RFCv2] Realtek SMI RTL836x DSA driver Thread-Topic: [OpenWrt-Devel] [PATCH 0/4 RFCv2] Realtek SMI RTL836x DSA driver Thread-Index: AQHT9qxrIfvGiYbFK0ePOsn83432r6RFc82AgADy1wCAADv4AIAAaXKAgAAEbgA= Date: Tue, 29 May 2018 18:57:42 +0000 Message-ID: <6FB2D569-87D4-47A9-AB6D-51B85720B6DA@darbyshire-bryant.me.uk> References: <20180528174752.6806-1-linus.walleij@linaro.org> <20180528182037.GC27177@lunn.ch> <CACRpkdbnO4vhGHTodkMkP+Zgrr71jp2pGuyXCg03YzjK1D1NTw@mail.gmail.com> <20180529122424.GC10919@lunn.ch> <CACRpkdbem_jTe6cQwTeTi9Uhk2B88rGENePZvjbsq38mfvcs0A@mail.gmail.com> In-Reply-To: <CACRpkdbem_jTe6cQwTeTi9Uhk2B88rGENePZvjbsq38mfvcs0A@mail.gmail.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=kevin@darbyshire-bryant.me.uk; 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charset=us-ascii > On 29 May 2018, at 19:41, Linus Walleij <linus.walleij@linaro.org> = wrote: >=20 > On Tue, May 29, 2018 at 2:24 PM, Andrew Lunn <andrew@lunn.ch> wrote: >=20 >> Did you look at the switch end? I found a datasheet for the >> 8366/8369. Register at 0x0050, P8GCR. It has two bits for RGMII >> delays. >=20 > Unfortunately this datasheet is not applicable to RTL8366RB. >=20 > RTL documentation and model numbers are a complete mess > around the time when this chip came out, unfortunately... I even > started to implement using that datasheet and had to toss a bunch > of stuff away. >=20 > There might not even be a proper datasheet for RTL8366RB, > I'm afraid. The best we have is different (3 different AFAICT) > vendor code drops. Here is one drop over at DD-WRT: > = https://svn.dd-wrt.com//browser/src/linux/universal/linux-3.2/drivers/net/= ethernet/raeth/rb >=20 > As you can see, the RTL8366RB vendor driver consists of > a hacked version of their RTL8368S driver, so apparently those > two ASICs are similar, they even kept the same filenames. >=20 > For example the register defintions: > = https://svn.dd-wrt.com/browser/src/linux/universal/linux-3.2/drivers/net/e= thernet/raeth/rb/rtl8368s_reg.h >=20 >> With RGMII delays, you have 3 'choices'. >>=20 >> 1) The hardware design includes the delay, by zig-zagging the clock >> line to make it longer. >> 2) The 'MAC' side does the delay. >> 3) The 'PHY' side does the delay. >>=20 >> I normally recommend the PHY side doing it, because that's what most >> board do. Gives us some consistency. But it does not really >> matter. Just make sure one side, and only once side is inserting the >> delays. >=20 > Makes sense! But I haven't found anything applicable in the > RTL8366RB registers. >=20 > There are some jam tables with magic values written all over > the place that have no documentation, I fear this is one of the > settings poked around with there. >=20 > However, even if this router did not come with any code for > the RTL8366RB driver, I disassembled the binary to verify > that they use the same magic jam table, so the ASIC is > initialized in the same way. >=20 > Yours, > Linus Walleij >=20 > _______________________________________________ > openwrt-devel mailing list > openwrt-devel@lists.openwrt.org > https://lists.openwrt.org/listinfo/openwrt-devel Oh lordy, that horrible device as exhibited in the netgear DGN3500. = Talk about magic values = https://git.openwrt.org/?p=3Dopenwrt/openwrt.git;a=3Dcommit;h=3D42120bd7f3= 23ff7170b32a5fd4674babd8b184bc Cheers, Kevin D-B 012C ACB2 28C6 C53E 9775 9123 B3A2 389B 9DE2 334A --Apple-Mail=_628A51B3-63A5-4F9C-81B3-A871A5F7BECF Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename=signature.asc Content-Type: application/pgp-signature; name=signature.asc Content-Description: Message signed with OpenPGP -----BEGIN PGP SIGNATURE----- iQIzBAEBCAAdFiEEASyssijGxT6XdZEjs6I4m53iM0oFAlsNoqQACgkQs6I4m53i M0pJNA/+Od2eT3vru2ww8uwxLGEc0n4TPEnWufIVHaX83WqWS5HkH6W+aezT/vpV unct87I0p8w+wYuIP0ckXXIU9LyFwKtcqW6qcHvAwJ98JpX6fXqXSvP4R79zjNBx mKI1jqTgaNubAiF7mjbmTxzftYZTsbDv5W8YysK9MBbWfWgu469RtJ24kqCyG9z2 00/CA1y8fcFQ3k7Yc2UD4Vsv8eiIplwmFySGsfps+rbVUrsWWlsAZxoDyDaQueKi LSFmGdAhCYTGUZPb5NJifcQZvpFrx99xKJVWBDOmWntnzucptbS7mlIED3peRfrg ypwRJMzqWTx8o4tqAaGBXDbYb9M6V1d+B/0d5DNxyXIhqI5oXzyvWQ0Grtywt7k7 wSoVtpQafuBFR2gZYWdhEB444mKWVvTGkB1kDbfXkd4IwtRGQ2n/Iev+gteDVzTn XRHDqbqM9XMjvlGrrKf2KHsWav2ndELZXSwqn33EArK+c5ruAEhDDfrrhovW5ayE N5mFdDrBcr1lmr45dcxZ6uN16zbwnwCYMII7X26VWL8mgPnxHBpPdNCIKSIfXjkm XUqn4vNSB4oHkvvd4LZe5CZSbsnxiIpWdUvA5tzQu2vKg/sj4tZojg1/8u4abf7i ZDQeOYFGJT4w/0iXr57yy7nBPC5XF4NV5DvxqCuFV54aBGmMRVw= =jI5V -----END PGP SIGNATURE----- --Apple-Mail=_628A51B3-63A5-4F9C-81B3-A871A5F7BECF-- ]