<div dir="ltr">Is it ever going to be added so this endless spam can end?<br><div><br></div></div><div class="gmail_extra"><br><div class="gmail_quote">On 8 May 2017 at 22:12, Linus Walleij <span dir="ltr"><<a href="mailto:linus.walleij@linaro.org" target="_blank">linus.walleij@linaro.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">The Cortina Systems Gemini (SL3516/CS3516) has an on-chip clock<br>
controller that derive all clocks from a single crystal, using some<br>
documented and some undocumented PLLs, half dividers, counters and<br>
gates. This is a best attempt to construct a clock driver for the<br>
clocks so at least we can gate off unused hardware and driver the<br>
PCI bus clock.<br>
<br>
Signed-off-by: Linus Walleij <<a href="mailto:linus.walleij@linaro.org">linus.walleij@linaro.org</a>><br>
---<br>
ChangeLog v1->v2:<br>
- Move the clock controller to be part of the syscon node. No<br>
need for a separate child node for this.<br>
---<br>
drivers/clk/Kconfig | 7 +<br>
drivers/clk/Makefile | 1 +<br>
drivers/clk/clk-gemini.c | 358 ++++++++++++++++++++++++++++++<wbr>+++++++++++++++++<br>
3 files changed, 366 insertions(+)<br>
create mode 100644 drivers/clk/clk-gemini.c<br>
<br>
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig<br>
index 9356ab4b7d76..9e7619f9bf0e 100644<br>
--- a/drivers/clk/Kconfig<br>
+++ b/drivers/clk/Kconfig<br>
@@ -118,6 +118,13 @@ config COMMON_CLK_CS2000_CP<br>
help<br>
If you say yes here you get support for the CS2000 clock multiplier.<br>
<br>
+config COMMON_CLK_GEMINI<br>
+ bool "Clock driver for Cortina Systems Gemini SoC"<br>
+ select MFD_SYSCON<br>
+ ---help---<br>
+ This driver supports the SoC clocks on the Cortina Systems Gemini<br>
+ platform, also known as SL3516 or CS3516.<br>
+<br>
config COMMON_CLK_S2MPS11<br>
tristate "Clock driver for S2MPS1X/S5M8767 MFD"<br>
depends on MFD_SEC_CORE || COMPILE_TEST<br>
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile<br>
index 92c12b86c2e8..e100d911a554 100644<br>
--- a/drivers/clk/Makefile<br>
+++ b/drivers/clk/Makefile<br>
@@ -25,6 +25,7 @@ obj-$(CONFIG_COMMON_CLK_<wbr>CDCE925) += clk-cdce925.o<br>
obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o<br>
obj-$(CONFIG_COMMON_CLK_<wbr>CS2000_CP) += clk-cs2000-cp.o<br>
obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o<br>
+obj-$(CONFIG_COMMON_CLK_<wbr>GEMINI) += clk-gemini.o<br>
obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o<br>
obj-$(CONFIG_COMMON_CLK_<wbr>MAX77686) += clk-max77686.o<br>
obj-$(CONFIG_ARCH_MB86S7X) += clk-mb86s7x.o<br>
diff --git a/drivers/clk/clk-gemini.c b/drivers/clk/clk-gemini.c<br>
new file mode 100644<br>
index 000000000000..340c2570f24e<br>
--- /dev/null<br>
+++ b/drivers/clk/clk-gemini.c<br>
@@ -0,0 +1,358 @@<br>
+/*<br>
+ * Cortina Gemini Clock Controller driver<br>
+ * Copyright (c) 2017 Linus Walleij <<a href="mailto:linus.walleij@linaro.org">linus.walleij@linaro.org</a>><br>
+ */<br>
+<br>
+#define pr_fmt(fmt) "clk-gemini: " fmt<br>
+<br>
+#include <linux/clkdev.h><br>
+#include <linux/slab.h><br>
+#include <linux/err.h><br>
+#include <linux/io.h><br>
+#include <linux/clk-provider.h><br>
+#include <linux/of.h><br>
+#include <linux/of_address.h><br>
+#include <linux/mfd/syscon.h><br>
+#include <linux/regmap.h><br>
+#include <dt-bindings/clock/cortina,<wbr>gemini-clock.h><br>
+<br>
+/* Globally visible clocks */<br>
+static DEFINE_SPINLOCK(gemini_clk_<wbr>lock);<br>
+static struct clk *gemini_clks[GEMINI_NUM_CLKS];<br>
+static struct clk_onecell_data gemini_clk_data;<br>
+<br>
+#define GEMINI_GLOBAL_STATUS 0x04<br>
+#define PLL_OSC_SEL BIT(30)<br>
+#define AHBSPEED_SHIFT (15)<br>
+#define AHBSPEED_MASK 0x07<br>
+#define CPU_AHB_RATIO_SHIFT (18)<br>
+#define CPU_AHB_RATIO_MASK 0x03<br>
+<br>
+#define GEMINI_GLOBAL_PLL_CONTROL 0x08<br>
+<br>
+#define GEMINI_GLOBAL_MISC_CONTROL 0x30<br>
+#define PCI_CLK_66MHZ BIT(18)<br>
+#define PCI_CLK_OE BIT(17)<br>
+<br>
+#define GEMINI_GLOBAL_CLOCK_CONTROL 0x34<br>
+#define PCI_CLKRUN_EN BIT(16)<br>
+#define TVC_HALFDIV_SHIFT (24)<br>
+#define TVC_HALFDIV_MASK 0x1f<br>
+#define SECURITY_CLK_SEL BIT(29)<br>
+<br>
+#define GEMINI_GLOBAL_PCI_DLL_CONTROL 0x44<br>
+#define PCI_DLL_BYPASS BIT(31)<br>
+#define PCI_DLL_TAP_SEL_MASK 0x1f<br>
+<br>
+struct gemini_gate_data {<br>
+ u8 bit_idx;<br>
+ const char *name;<br>
+ const char *parent_name;<br>
+ unsigned long flags;<br>
+};<br>
+<br>
+/**<br>
+ * struct clk_gemini_pci - Gemini PCI clock<br>
+ * @hw: corresponding clock hardware entry<br>
+ * @map: regmap to access the registers<br>
+ * @rate: current rate<br>
+ */<br>
+struct clk_gemini_pci {<br>
+ struct clk_hw hw;<br>
+ struct regmap *map;<br>
+ unsigned long rate;<br>
+};<br>
+<br>
+/*<br>
+ * FIXME: some clocks are marked as CLK_IGNORE_UNUSED: this is<br>
+ * because their kernel drivers lack proper clock handling so we<br>
+ * need to avoid them being gated off by default. Remove this as<br>
+ * the drivers get fixed to handle clocks properly.<br>
+ *<br>
+ * The DDR controller may never have a driver, but certainly must<br>
+ * not be gated off.<br>
+ */<br>
+static const struct gemini_gate_data gemini_gates[] __initconst = {<br>
+ { 1, "security-gate", "secdiv", 0 },<br>
+ { 2, "gmac0-gate", "ahb", 0 },<br>
+ { 3, "gmac1-gate", "ahb", 0 },<br>
+ { 4, "sata0-gate", "ahb", 0 },<br>
+ { 5, "sata1-gate", "ahb", 0 },<br>
+ { 6, "usb0-gate", "ahb", 0 },<br>
+ { 7, "usb1-gate", "ahb", 0 },<br>
+ { 8, "ide-gate", "ahb", 0 },<br>
+ { 9, "pci-gate", "ahb", 0 },<br>
+ { 10, "ddr-gate", "ahb", CLK_IGNORE_UNUSED },<br>
+ { 11, "flash-gate", "ahb", CLK_IGNORE_UNUSED },<br>
+ { 12, "tvc-gate", "ahb", 0 },<br>
+ { 13, "boot-gate", "apb", 0 },<br>
+};<br>
+<br>
+#define to_pciclk(_hw) container_of(_hw, struct clk_gemini_pci, hw)<br>
+<br>
+static unsigned long gemini_pci_recalc_rate(struct clk_hw *hw,<br>
+ unsigned long parent_rate)<br>
+{<br>
+ struct clk_gemini_pci *pciclk = to_pciclk(hw);<br>
+ u32 val;<br>
+ int ret;<br>
+<br>
+ ret = regmap_read(pciclk->map, GEMINI_GLOBAL_MISC_CONTROL, &val);<br>
+ if (ret)<br>
+ return ret;<br>
+ if (val & PCI_CLK_66MHZ)<br>
+ return 66000000;<br>
+ return 33000000;<br>
+}<br>
+<br>
+static long gemini_pci_round_rate(struct clk_hw *hw, unsigned long rate,<br>
+ unsigned long *prate)<br>
+{<br>
+ /* We support 33 and 66 MHz */<br>
+ if (rate < 48000000)<br>
+ return 33000000;<br>
+ return 66000000;<br>
+}<br>
+<br>
+static int gemini_pci_set_rate(struct clk_hw *hw, unsigned long rate,<br>
+ unsigned long parent_rate)<br>
+{<br>
+ struct clk_gemini_pci *pciclk = to_pciclk(hw);<br>
+<br>
+ if (rate == 33000000)<br>
+ return regmap_update_bits(pciclk-><wbr>map,<br>
+ GEMINI_GLOBAL_MISC_CONTROL,<br>
+ PCI_CLK_66MHZ, 0);<br>
+ if (rate == 66000000)<br>
+ return regmap_update_bits(pciclk-><wbr>map,<br>
+ GEMINI_GLOBAL_MISC_CONTROL,<br>
+ 0, PCI_CLK_66MHZ);<br>
+ return -EINVAL;<br>
+}<br>
+<br>
+static int gemini_pci_enable(struct clk_hw *hw)<br>
+{<br>
+ struct clk_gemini_pci *pciclk = to_pciclk(hw);<br>
+<br>
+ regmap_update_bits(pciclk-><wbr>map, GEMINI_GLOBAL_CLOCK_CONTROL,<br>
+ 0, PCI_CLKRUN_EN);<br>
+ regmap_update_bits(pciclk-><wbr>map,<br>
+ GEMINI_GLOBAL_MISC_CONTROL,<br>
+ 0, PCI_CLK_OE);<br>
+ return 0;<br>
+}<br>
+<br>
+static void gemini_pci_disable(struct clk_hw *hw)<br>
+{<br>
+ struct clk_gemini_pci *pciclk = to_pciclk(hw);<br>
+<br>
+ regmap_update_bits(pciclk-><wbr>map,<br>
+ GEMINI_GLOBAL_MISC_CONTROL,<br>
+ PCI_CLK_OE, 0);<br>
+ regmap_update_bits(pciclk-><wbr>map, GEMINI_GLOBAL_CLOCK_CONTROL,<br>
+ PCI_CLKRUN_EN, 0);<br>
+}<br>
+<br>
+static int gemini_pci_is_enabled(struct clk_hw *hw)<br>
+{<br>
+ struct clk_gemini_pci *pciclk = to_pciclk(hw);<br>
+ int ret;<br>
+ unsigned int val;<br>
+<br>
+ ret = regmap_read(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL, &val);<br>
+ if (ret)<br>
+ return ret;<br>
+<br>
+ return !!(val & PCI_CLKRUN_EN);<br>
+}<br>
+<br>
+static const struct clk_ops gemini_pci_clk_ops = {<br>
+ .recalc_rate = gemini_pci_recalc_rate,<br>
+ .round_rate = gemini_pci_round_rate,<br>
+ .set_rate = gemini_pci_set_rate,<br>
+ .enable = gemini_pci_enable,<br>
+ .disable = gemini_pci_disable,<br>
+ .is_enabled = gemini_pci_is_enabled,<br>
+};<br>
+<br>
+static struct clk *gemini_pci_clk_setup(const char *name,<br>
+ const char *parent_name,<br>
+ struct regmap *map)<br>
+{<br>
+ struct clk_gemini_pci *pciclk;<br>
+ struct clk_init_data init;<br>
+ struct clk *clk;<br>
+<br>
+ pciclk = kzalloc(sizeof(*pciclk), GFP_KERNEL);<br>
+ if (!pciclk)<br>
+ return ERR_PTR(-ENOMEM);<br>
+<br>
+ <a href="http://init.name" rel="noreferrer" target="_blank">init.name</a> = name;<br>
+ init.ops = &gemini_pci_clk_ops;<br>
+ init.flags = 0;<br>
+ init.parent_names = (parent_name ? &parent_name : NULL);<br>
+ init.num_parents = (parent_name ? 1 : 0);<br>
+ pciclk->map = map;<br>
+ pciclk->hw.init = &init;<br>
+<br>
+ clk = clk_register(NULL, &pciclk->hw);<br>
+ if (IS_ERR(clk))<br>
+ kfree(pciclk);<br>
+<br>
+ return clk;<br>
+}<br>
+<br>
+static void __init gemini_cc_init(struct device_node *np)<br>
+{<br>
+ void __iomem *base;<br>
+ struct regmap *map;<br>
+ struct clk *clk;<br>
+ unsigned int mult, div;<br>
+ unsigned long freq;<br>
+ u32 val;<br>
+ int ret;<br>
+ int i;<br>
+<br>
+ /* Remap the system controller for the exclusive register */<br>
+ base = of_iomap(np, 0);<br>
+ if (!base) {<br>
+ pr_err("no memory base\n");<br>
+ return;<br>
+ }<br>
+ map = syscon_node_to_regmap(np);<br>
+ if (IS_ERR(map)) {<br>
+ pr_err("no syscon regmap\n");<br>
+ return;<br>
+ }<br>
+<br>
+ /* RTC clock 32768 Hz */<br>
+ clk = clk_register_fixed_rate(NULL, "rtc", NULL, CLK_IGNORE_UNUSED,<br>
+ 32768);<br>
+ gemini_clks[GEMINI_CLK_RTC] = clk;<br>
+<br>
+ ret = regmap_read(map, GEMINI_GLOBAL_STATUS, &val);<br>
+ if (ret) {<br>
+ pr_err("failed to read global status register\n");<br>
+ return;<br>
+ }<br>
+<br>
+ /*<br>
+ * XTAL is the crystal oscillator, 60 or 30 MHz selected from<br>
+ * strap pin E6<br>
+ */<br>
+ if (val & PLL_OSC_SEL)<br>
+ freq = 30000000;<br>
+ else<br>
+ freq = 60000000;<br>
+ clk = clk_register_fixed_rate(NULL, "xtal", NULL, CLK_IGNORE_UNUSED,<br>
+ freq);<br>
+ pr_info("main crystal @%lu MHz\n", (freq/1000000));<br>
+<br>
+ /* VCO clock derived from the crystal */<br>
+ mult = 13 + ((val >> AHBSPEED_SHIFT) & AHBSPEED_MASK);<br>
+ div = 2;<br>
+ /* If we run on 30 Mhz crystal we have to multiply with two */<br>
+ if (val & PLL_OSC_SEL)<br>
+ mult *= 2;<br>
+ clk = clk_register_fixed_factor(<wbr>NULL, "vco", "xtal", CLK_IGNORE_UNUSED,<br>
+ mult, div);<br>
+<br>
+ /* The AHB clock is always 1/3 of the VCO */<br>
+ clk = clk_register_fixed_factor(<wbr>NULL, "ahb", "vco",<br>
+ CLK_IGNORE_UNUSED, 1, 3);<br>
+ gemini_clks[GEMINI_CLK_AHB] = clk;<br>
+<br>
+ /* The APB clock is always 1/6 of the AHB */<br>
+ clk = clk_register_fixed_factor(<wbr>NULL, "apb", "ahb",<br>
+ CLK_IGNORE_UNUSED, 1, 6);<br>
+ gemini_clks[GEMINI_CLK_APB] = clk;<br>
+<br>
+ /* CPU clock derived as a fixed ratio from the AHB clock */<br>
+ switch ((val >> CPU_AHB_RATIO_SHIFT) & CPU_AHB_RATIO_MASK) {<br>
+ case 0x0:<br>
+ /* 1x */<br>
+ mult = 1;<br>
+ div = 1;<br>
+ break;<br>
+ case 0x1:<br>
+ /* 1.5x */<br>
+ mult = 3;<br>
+ div = 2;<br>
+ break;<br>
+ case 0x2:<br>
+ /* 1.85x */<br>
+ mult = 24;<br>
+ div = 13;<br>
+ break;<br>
+ case 0x3:<br>
+ /* 2x */<br>
+ mult = 2;<br>
+ div = 1;<br>
+ break;<br>
+ }<br>
+ clk = clk_register_fixed_factor(<wbr>NULL, "cpu", "ahb",<br>
+ CLK_IGNORE_UNUSED, mult, div);<br>
+ gemini_clks[GEMINI_CLK_CPU] = clk;<br>
+<br>
+ /* Security clock is 1:1 or 0.75 of APB */<br>
+ ret = regmap_read(map, GEMINI_GLOBAL_CLOCK_CONTROL, &val);<br>
+ if (ret) {<br>
+ pr_err("failed to read global clock control register\n");<br>
+ return;<br>
+ }<br>
+ if (val & SECURITY_CLK_SEL) {<br>
+ mult = 1;<br>
+ div = 1;<br>
+ } else {<br>
+ mult = 3;<br>
+ div = 4;<br>
+ }<br>
+ clk = clk_register_fixed_factor(<wbr>NULL, "secdiv", "ahb",<br>
+ 0, mult, div);<br>
+<br>
+ /*<br>
+ * These are the leaf gates, at boot no clocks are gated.<br>
+ */<br>
+ for (i = 0; i < ARRAY_SIZE(gemini_gates); i++) {<br>
+ const struct gemini_gate_data *gd;<br>
+<br>
+ gd = &gemini_gates[i];<br>
+ gemini_clks[GEMINI_CLK_GATES + i] =<br>
+ clk_register_gate(NULL, gd->name,<br>
+ gd->parent_name,<br>
+ gd->flags,<br>
+ base + GEMINI_GLOBAL_CLOCK_CONTROL,<br>
+ gd->bit_idx,<br>
+ CLK_GATE_SET_TO_DISABLE,<br>
+ &gemini_clk_lock);<br>
+ }<br>
+<br>
+ /*<br>
+ * The TV Interface Controller has a 5-bit half divider register.<br>
+ * This clock is supposed to be 27MHz as this is an exact multiple<br>
+ * of PAL and NTSC frequencies. The register is undocumented :(<br>
+ * FIXME: figure out the parent and how the divider works.<br>
+ */<br>
+ mult = 1;<br>
+ div = ((val >> TVC_HALFDIV_SHIFT) & TVC_HALFDIV_MASK);<br>
+ pr_debug("TVC half divider value = %d\n", div);<br>
+ div += 1;<br>
+ clk = clk_register_fixed_rate(NULL, "tvcdiv", "xtal", 0, 27000000);<br>
+ gemini_clks[GEMINI_CLK_TVC] = clk;<br>
+<br>
+ /* FIXME: very unclear what the parent is */<br>
+ clk = gemini_pci_clk_setup("PCI", "xtal", map);<br>
+ gemini_clks[GEMINI_CLK_PCI] = clk;<br>
+<br>
+ /* FIXME: very unclear what the parent is */<br>
+ clk = clk_register_fixed_rate(NULL, "uart", "xtal", CLK_IGNORE_UNUSED,<br>
+ 48000000);<br>
+ gemini_clks[GEMINI_CLK_UART] = clk;<br>
+<br>
+ /* Register the clocks to be accessed by the device tree */<br>
+ gemini_clk_data.clks = gemini_clks;<br>
+ gemini_clk_data.clk_num = ARRAY_SIZE(gemini_clks);<br>
+ of_clk_add_provider(np, of_clk_src_onecell_get, &gemini_clk_data);<br>
+}<br>
+CLK_OF_DECLARE_DRIVER(gemini_<wbr>cc, "cortina,gemini-clock-<wbr>controller",<br>
+ gemini_cc_init);<br>
<span class="HOEnZb"><font color="#888888">--<br>
2.9.3<br>
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</font></span></blockquote></div><br></div>