From: Sven Eckelmann Date: Tue, 8 Mar 2016 16:20:54 +0100 Subject: [PATCH] Print PLL/ETH_CFG INFOs --- target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c index 6445023..f4ec450 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c @@ -377,8 +377,11 @@ static void qca955x_set_speed_xmii(int speed) { void __iomem *base; u32 val = ath79_get_eth_pll(0, speed); + u32 t; base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); + t = __raw_readl(base + QCA955X_PLL_ETH_XMII_CONTROL_REG); + printk("XXXXXX %s:%u old %08x new %08x\n", __func__, __LINE__, t, val); __raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG); iounmap(base); } @@ -387,8 +390,11 @@ static void qca955x_set_speed_sgmii(int speed) { void __iomem *base; u32 val = ath79_get_eth_pll(1, speed); + u32 t; base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); + t = __raw_readl(base + QCA955X_PLL_ETH_SGMII_CONTROL_REG); + printk("XXXXXX %s:%u old %08x new %08x\n", __func__, __LINE__, t, val); __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG); iounmap(base); } @@ -855,6 +861,7 @@ void __init ath79_setup_qca955x_eth_cfg(u32 mask, base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE); t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG); + printk("QCA955X_GMAC_REG_ETH_CFG-pre %08x\n", t); t &= ~m; t |= mask; @@ -863,6 +870,8 @@ void __init ath79_setup_qca955x_eth_cfg(u32 mask, t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT; t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT; + printk("QCA955X_GMAC_REG_ETH_CFG-post %08x\n", t); + __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG); iounmap(base);