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Dear Mingyu,<br>
<br>
It works perfectly after adding the second spi clock:<br>
<a class="moz-txt-link-freetext" href="https://gist.github.com/Noltari/9231b6c73c3b36e681ef">https://gist.github.com/Noltari/9231b6c73c3b36e681ef</a><br>
<br>
I'm sorry but I couldn't test this before.<br>
<br>
Regards,<br>
Álvaro.<br>
<br>
<div class="moz-cite-prefix">El 23/11/2015 a las 2:41, Mingyu Li
escribió:<br>
</div>
<blockquote
cite="mid:CAJ0DAD+AZV4FWKHoneNoW8oxJN1sHD6iRp+Y_Hr7P1wZiFaiWw@mail.gmail.com"
type="cite">
<div dir="ltr">
<div>Dear Sir.<br>
<br>
</div>
<div>you need to modify kernel file at
"arch/mips/ralink/rt305x.c"<br>
</div>
<div>add the code below.<br>
<br>
ralink_clk_add("10000b00.spi", sys_rate);<br>
+ ralink_clk_add("10000b40.spi", sys_rate);<br>
ralink_clk_add("10000100.timer", wdt_rate);<br>
<br>
</div>
<div>please let me know if the second spi works. if works<br>
</div>
<div>i will commit a patch about the second spi clock include <br>
all other targets.<br>
thanks.<br>
</div>
<div><br>
</div>
Best Regards.<br>
</div>
<div class="gmail_extra"><br>
<div class="gmail_quote">2015-11-23 3:08 GMT+08:00 John Crispin
<span dir="ltr"><<a moz-do-not-send="true"
href="mailto:blogic@openwrt.org" target="_blank">blogic@openwrt.org</a>></span>:<br>
<blockquote class="gmail_quote" style="margin:0 0 0
.8ex;border-left:1px #ccc solid;padding-left:1ex"><span
class=""><br>
<br>
On 22/11/2015 16:15, Álvaro Fernández Rojas wrote:<br>
> Hello guys,<br>
><br>
> I've just tested this patch on my VoCore after it was
applied on r47580.<br>
> I had to make the following changes:<br>
> <a moz-do-not-send="true"
href="https://github.com/openwrt-es/openwrt/commit/e040cf00441e973978a6c168b346b13e33f37853"
rel="noreferrer" target="_blank">https://github.com/openwrt-es/openwrt/commit/e040cf00441e973978a6c168b346b13e33f37853</a><br>
><br>
><br>
> However, I'm getting the following error: "spi-rt2880
10000b40.spi:<br>
> unable to get SYS clock"<br>
> <a moz-do-not-send="true"
href="https://gist.github.com/Noltari/7629d3384fe421517336"
rel="noreferrer" target="_blank">https://gist.github.com/Noltari/7629d3384fe421517336</a><br>
><br>
> Did anyone actually test this with both spi nodes
enabled?<br>
><br>
> Regards,<br>
> Álvaro.<br>
<br>
</span>i only compile tested it.<br>
<span class="HOEnZb"><font color="#888888"><br>
John<br>
</font></span>
<div class="HOEnZb">
<div class="h5"><br>
><br>
> El 08/10/2015 a las 16:16, Michael Lee escribió:<br>
>> Signed-off-by: Michael Lee <<a
moz-do-not-send="true" href="mailto:igvtee@gmail.com"><a class="moz-txt-link-abbreviated" href="mailto:igvtee@gmail.com">igvtee@gmail.com</a></a>><br>
>> ---<br>
>> target/linux/ramips/dts/mt7620a.dtsi
| 32 +-<br>
>> target/linux/ramips/dts/mt7620n.dtsi
| 32 +-<br>
>> target/linux/ramips/dts/rt3050.dtsi
| 6 +-<br>
>> target/linux/ramips/dts/rt3352.dtsi
| 31 +-<br>
>> target/linux/ramips/dts/rt3883.dtsi
| 25 +-<br>
>> target/linux/ramips/dts/rt5350.dtsi
| 29 +-<br>
>> .../0051-rt5350-spi-second-device.patch
| 368<br>
>> ---------------------<br>
>> 7 files changed, 143 insertions(+), 380
deletions(-)<br>
>> delete mode 100644<br>
>>
target/linux/ramips/patches-3.18/0051-rt5350-spi-second-device.patch<br>
>><br>
>> diff --git
a/target/linux/ramips/dts/mt7620a.dtsi<br>
>> b/target/linux/ramips/dts/mt7620a.dtsi<br>
>> index 026e745..448df75 100644<br>
>> --- a/target/linux/ramips/dts/mt7620a.dtsi<br>
>> +++ b/target/linux/ramips/dts/mt7620a.dtsi<br>
>> @@ -20,6 +20,11 @@<br>
>> compatible =
"mti,cpu-interrupt-controller";<br>
>> };<br>
>> + aliases {<br>
>> + spi0 = &spi0;<br>
>> + spi1 = &spi1;<br>
>> + };<br>
>> +<br>
>> palmbus@10000000 {<br>
>> compatible = "palmbus";<br>
>> reg = <0x10000000 0x200000>;<br>
>> @@ -202,9 +207,9 @@<br>
>> status = "disabled";<br>
>> };<br>
>> - spi@b00 {<br>
>> + spi0: spi@b00 {<br>
>> compatible =
"ralink,mt7620a-spi", "ralink,rt2880-spi";<br>
>> - reg = <0xb00 0x100>;<br>
>> + reg = <0xb00 0x40>;<br>
>> resets = <&rstctrl
18>;<br>
>> reset-names = "spi";<br>
>> @@ -218,6 +223,22 @@<br>
>> pinctrl-0 =
<&spi_pins>;<br>
>> };<br>
>> + spi1: spi@b40 {<br>
>> + compatible = "ralink,rt2880-spi";<br>
>> + reg = <0xb40 0x60>;<br>
>> +<br>
>> + resets = <&rstctrl 18>;<br>
>> + reset-names = "spi";<br>
>> +<br>
>> + #address-cells = <1>;<br>
>> + #size-cells = <1>;<br>
>> +<br>
>> + status = "disabled";<br>
>> +<br>
>> + pinctrl-names = "default";<br>
>> + pinctrl-0 = <&spi_cs1>;<br>
>> + };<br>
>> +<br>
>> uartlite@c00 {<br>
>> compatible =
"ralink,mt7620a-uart",<br>
>> "ralink,rt2880-uart", "ns16550a";<br>
>> reg = <0xc00 0x100>;<br>
>> @@ -305,6 +326,13 @@<br>
>> };<br>
>> };<br>
>> + spi_cs1: spi1 {<br>
>> + spi1 {<br>
>> + ralink,group = "spi_cs1";<br>
>> + ralink,function = "spi_cs1";<br>
>> + };<br>
>> + };<br>
>> +<br>
>> i2c_pins: i2c {<br>
>> i2c {<br>
>> ralink,group = "i2c";<br>
>> diff --git
a/target/linux/ramips/dts/mt7620n.dtsi<br>
>> b/target/linux/ramips/dts/mt7620n.dtsi<br>
>> index b1586ec..a3132b8 100644<br>
>> --- a/target/linux/ramips/dts/mt7620n.dtsi<br>
>> +++ b/target/linux/ramips/dts/mt7620n.dtsi<br>
>> @@ -20,6 +20,11 @@<br>
>> compatible =
"mti,cpu-interrupt-controller";<br>
>> };<br>
>> + aliases {<br>
>> + spi0 = &spi0;<br>
>> + spi1 = &spi1;<br>
>> + };<br>
>> +<br>
>> palmbus@10000000 {<br>
>> compatible = "palmbus";<br>
>> reg = <0x10000000 0x200000>;<br>
>> @@ -154,9 +159,9 @@<br>
>> status = "disabled";<br>
>> };<br>
>> - spi@b00 {<br>
>> + spi0: spi@b00 {<br>
>> compatible =
"ralink,mt7620a-spi", "ralink,rt2880-spi";<br>
>> - reg = <0xb00 0x100>;<br>
>> + reg = <0xb00 0x40>;<br>
>> resets = <&rstctrl
18>;<br>
>> reset-names = "spi";<br>
>> @@ -170,6 +175,22 @@<br>
>> pinctrl-0 =
<&spi_pins>;<br>
>> };<br>
>> + spi1: spi@b40 {<br>
>> + compatible = "ralink,rt2880-spi";<br>
>> + reg = <0xb40 0x60>;<br>
>> +<br>
>> + resets = <&rstctrl 18>;<br>
>> + reset-names = "spi";<br>
>> +<br>
>> + #address-cells = <1>;<br>
>> + #size-cells = <1>;<br>
>> +<br>
>> + status = "disabled";<br>
>> +<br>
>> + pinctrl-names = "default";<br>
>> + pinctrl-0 = <&spi_cs1>;<br>
>> + };<br>
>> +<br>
>> uartlite@c00 {<br>
>> compatible =
"ralink,mt7620a-uart",<br>
>> "ralink,rt2880-uart", "ns16550a";<br>
>> reg = <0xc00 0x100>;<br>
>> @@ -213,6 +234,13 @@<br>
>> };<br>
>> };<br>
>> + spi_cs1: spi1 {<br>
>> + spi1 {<br>
>> + ralink,group = "spi_cs1";<br>
>> + ralink,function = "spi_cs1";<br>
>> + };<br>
>> + };<br>
>> +<br>
>> uartlite_pins: uartlite {<br>
>> uart {<br>
>> ralink,group = "uartlite";<br>
>> diff --git
a/target/linux/ramips/dts/rt3050.dtsi<br>
>> b/target/linux/ramips/dts/rt3050.dtsi<br>
>> index 27e4179..7f0fb4a 100644<br>
>> --- a/target/linux/ramips/dts/rt3050.dtsi<br>
>> +++ b/target/linux/ramips/dts/rt3050.dtsi<br>
>> @@ -13,6 +13,10 @@<br>
>> bootargs = "console=ttyS0,57600";<br>
>> };<br>
>> + aliases {<br>
>> + spi0 = &spi0;<br>
>> + };<br>
>> +<br>
>> cpuintc: cpuintc@0 {<br>
>> #address-cells = <0>;<br>
>> #interrupt-cells = <1>;<br>
>> @@ -144,7 +148,7 @@<br>
>> status = "disabled";<br>
>> };<br>
>> - spi@b00 {<br>
>> + spi0: spi@b00 {<br>
>> compatible = "ralink,rt3050-spi",
"ralink,rt2880-spi";<br>
>> reg = <0xb00 0x100>;<br>
>> diff --git
a/target/linux/ramips/dts/rt3352.dtsi<br>
>> b/target/linux/ramips/dts/rt3352.dtsi<br>
>> index b04845c..ffb9336 100644<br>
>> --- a/target/linux/ramips/dts/rt3352.dtsi<br>
>> +++ b/target/linux/ramips/dts/rt3352.dtsi<br>
>> @@ -20,6 +20,11 @@<br>
>> compatible =
"mti,cpu-interrupt-controller";<br>
>> };<br>
>> + aliases {<br>
>> + spi0 = &spi0;<br>
>> + spi1 = &spi1;<br>
>> + };<br>
>> +<br>
>> palmbus@10000000 {<br>
>> compatible = "palmbus";<br>
>> reg = <0x10000000 0x200000>;<br>
>> @@ -140,9 +145,9 @@<br>
>> status = "disabled";<br>
>> };<br>
>> - spi@b00 {<br>
>> + spi0: spi@b00 {<br>
>> compatible = "ralink,rt3352-spi",
"ralink,rt2880-spi";<br>
>> - reg = <0xb00 0x100>;<br>
>> + reg = <0xb00 0x40>;<br>
>> #address-cells = <1>;<br>
>> #size-cells = <0>;<br>
>> @@ -155,6 +160,21 @@<br>
>> status = "disabled";<br>
>> };<br>
>> + spi1: spi@b40 {<br>
>> + compatible = "ralink,rt3352-spi",
"ralink,rt2880-spi";<br>
>> + reg = <0xb40 0x60>;<br>
>> + #address-cells = <1>;<br>
>> + #size-cells = <1>;<br>
>> +<br>
>> + resets = <&rstctrl 18>;<br>
>> + reset-names = "spi";<br>
>> +<br>
>> + pinctrl-names = "default";<br>
>> + pinctrl-0 = <&spi_cs1>;<br>
>> +<br>
>> + status = "disabled";<br>
>> + };<br>
>> +<br>
>> uartlite@c00 {<br>
>> compatible =
"ralink,rt3352-uart", "ralink,rt2880-uart",<br>
>> "ns16550a";<br>
>> reg = <0xc00 0x100>;<br>
>> @@ -188,6 +208,13 @@<br>
>> };<br>
>> };<br>
>> + spi_cs1: spi1 {<br>
>> + spi1 {<br>
>> + ralink,group = "spi_cs1";<br>
>> + ralink,function = "spi_cs1";<br>
>> + };<br>
>> + };<br>
>> +<br>
>> uartlite_pins: uartlite {<br>
>> uart {<br>
>> ralink,group = "uartlite";<br>
>> diff --git
a/target/linux/ramips/dts/rt3883.dtsi<br>
>> b/target/linux/ramips/dts/rt3883.dtsi<br>
>> index dc26782..6592b3b 100644<br>
>> --- a/target/linux/ramips/dts/rt3883.dtsi<br>
>> +++ b/target/linux/ramips/dts/rt3883.dtsi<br>
>> @@ -15,6 +15,7 @@<br>
>> aliases {<br>
>> spi0 = &spi0;<br>
>> + spi1 = &spi1;<br>
>> };<br>
>> cpuintc: cpuintc@0 {<br>
>> @@ -166,7 +167,7 @@<br>
>> spi0: spi@b00 {<br>
>> compatible = "ralink,rt3883-spi",
"ralink,rt2880-spi";<br>
>> - reg = <0xb00 0x100>;<br>
>> + reg = <0xb00 0x40>;<br>
>> #address-cells = <1>;<br>
>> #size-cells = <0>;<br>
>> @@ -179,6 +180,21 @@<br>
>> status = "disabled";<br>
>> };<br>
>> + spi1: spi@b40 {<br>
>> + compatible = "ralink,rt3883-spi",
"ralink,rt2880-spi";<br>
>> + reg = <0xb40 0x60>;<br>
>> + #address-cells = <1>;<br>
>> + #size-cells = <0>;<br>
>> +<br>
>> + resets = <&rstctrl 18>;<br>
>> + reset-names = "spi";<br>
>> +<br>
>> + pinctrl-names = "default";<br>
>> + pinctrl-0 = <&spi_cs1>;<br>
>> +<br>
>> + status = "disabled";<br>
>> + };<br>
>> +<br>
>> uartlite@c00 {<br>
>> compatible =
"ralink,rt3883-uart", "ralink,rt2880-uart",<br>
>> "ns16550a";<br>
>> reg = <0xc00 0x100>;<br>
>> @@ -212,6 +228,13 @@<br>
>> };<br>
>> };<br>
>> + spi_cs1: spi1 {<br>
>> + spi1 {<br>
>> + ralink,group = "spi_cs1";<br>
>> + ralink,function = "spi_cs1";<br>
>> + };<br>
>> + };<br>
>> +<br>
>> uartlite_pins: uartlite {<br>
>> uart {<br>
>> ralink,group = "uartlite";<br>
>> diff --git
a/target/linux/ramips/dts/rt5350.dtsi<br>
>> b/target/linux/ramips/dts/rt5350.dtsi<br>
>> index 8dd06c8..66775c2 100644<br>
>> --- a/target/linux/ramips/dts/rt5350.dtsi<br>
>> +++ b/target/linux/ramips/dts/rt5350.dtsi<br>
>> @@ -20,6 +20,11 @@<br>
>> compatible =
"mti,cpu-interrupt-controller";<br>
>> };<br>
>> + aliases {<br>
>> + spi0 = &spi0;<br>
>> + spi1 = &spi1;<br>
>> + };<br>
>> +<br>
>> palmbus@10000000 {<br>
>> compatible = "palmbus";<br>
>> reg = <0x10000000 0x200000>;<br>
>> @@ -150,9 +155,25 @@<br>
>> status = "disabled";<br>
>> };<br>
>> - spi@b00 {<br>
>> - compatible = "ralink,rt5350-spi";<br>
>> - reg = <0xb00 0x100>;<br>
>> + spi0: spi@b00 {<br>
>> + compatible = "ralink,rt5350-spi",
"ralink,rt2880-spi";<br>
>> + reg = <0xb00 0x40>;<br>
>> +<br>
>> + resets = <&rstctrl 18>;<br>
>> + reset-names = "spi";<br>
>> +<br>
>> + #address-cells = <1>;<br>
>> + #size-cells = <1>;<br>
>> +<br>
>> + pinctrl-names = "default";<br>
>> + pinctrl-0 = <&spi_pins>;<br>
>> +<br>
>> + status = "disabled";<br>
>> + };<br>
>> +<br>
>> + spi1: spi@b40 {<br>
>> + compatible = "ralink,rt5350-spi",
"ralink,rt2880-spi";<br>
>> + reg = <0xb40 0x60>;<br>
>> resets = <&rstctrl
18>;<br>
>> reset-names = "spi";<br>
>> @@ -161,7 +182,7 @@<br>
>> #size-cells = <0>;<br>
>> pinctrl-names = "default";<br>
>> - pinctrl-0 = <&spi_pins
&spi_cs1>;<br>
>> + pinctrl-0 = <&spi_cs1>;<br>
>> status = "disabled";<br>
>> };<br>
>> diff --git<br>
>>
a/target/linux/ramips/patches-3.18/0051-rt5350-spi-second-device.patch<br>
>>
b/target/linux/ramips/patches-3.18/0051-rt5350-spi-second-device.patch<br>
>> deleted file mode 100644<br>
>> index 2da8151..0000000<br>
>> ---<br>
>>
a/target/linux/ramips/patches-3.18/0051-rt5350-spi-second-device.patch<br>
>> +++ /dev/null<br>
>> @@ -1,368 +0,0 @@<br>
>> -From 27b11d4f1888e1a3d6d75b46d4d5a4d86fc03891
Mon Sep 17 00:00:00 2001<br>
>> -From: John Crispin <<a
moz-do-not-send="true"
href="mailto:blogic@openwrt.org"><a class="moz-txt-link-abbreviated" href="mailto:blogic@openwrt.org">blogic@openwrt.org</a></a>><br>
>> -Date: Wed, 6 Aug 2014 10:53:40 +0200<br>
>> -Subject: [PATCH 51/57] SPI: MIPS: ralink: add
rt5350 dual SPI support<br>
>> -<br>
>> -Signed-off-by: John Crispin <<a
moz-do-not-send="true"
href="mailto:blogic@openwrt.org"><a class="moz-txt-link-abbreviated" href="mailto:blogic@openwrt.org">blogic@openwrt.org</a></a>><br>
>> -Signed-off-by: Felix Fietkau <<a
moz-do-not-send="true" href="mailto:nbd@openwrt.org"><a class="moz-txt-link-abbreviated" href="mailto:nbd@openwrt.org">nbd@openwrt.org</a></a>><br>
>> ----<br>
>> - drivers/spi/spi-rt2880.c | 218<br>
>> +++++++++++++++++++++++++++++++++++++++++++---<br>
>> - 1 file changed, 205 insertions(+), 13
deletions(-)<br>
>> -<br>
>> ---- a/drivers/spi/spi-rt2880.c<br>
>> -+++ b/drivers/spi/spi-rt2880.c<br>
>> -@@ -21,19 +21,25 @@<br>
>> - #include <linux/io.h><br>
>> - #include <linux/reset.h><br>
>> - #include <linux/spi/spi.h><br>
>> -+#include <linux/of_device.h><br>
>> - #include <linux/platform_device.h><br>
>> -<br>
>> -+#include <ralink_regs.h><br>
>> -+<br>
>> -+#define SPI_BPW_MASK(bits) BIT((bits) - 1)<br>
>> -+<br>
>> - #define DRIVER_NAME "spi-rt2880"<br>
>> --/* only one slave is supported*/<br>
>> --#define RALINK_NUM_CHIPSELECTS 1<br>
>> - /* in usec */<br>
>> - #define RALINK_SPI_WAIT_MAX_LOOP 2000<br>
>> -<br>
>> --#define RAMIPS_SPI_STAT 0x00<br>
>> --#define RAMIPS_SPI_CFG 0x10<br>
>> --#define RAMIPS_SPI_CTL 0x14<br>
>> --#define RAMIPS_SPI_DATA 0x20<br>
>> --#define RAMIPS_SPI_FIFO_STAT 0x38<br>
>> -+#define RAMIPS_SPI_DEV_OFFSET 0x40<br>
>> -+<br>
>> -+#define RAMIPS_SPI_STAT(cs) (0x00 +
(cs *<br>
>> RAMIPS_SPI_DEV_OFFSET))<br>
>> -+#define RAMIPS_SPI_CFG(cs) (0x10 + (cs
* RAMIPS_SPI_DEV_OFFSET))<br>
>> -+#define RAMIPS_SPI_CTL(cs) (0x14 + (cs
* RAMIPS_SPI_DEV_OFFSET))<br>
>> -+#define RAMIPS_SPI_DATA(cs) (0x20 +
(cs *<br>
>> RAMIPS_SPI_DEV_OFFSET))<br>
>> -+#define RAMIPS_SPI_FIFO_STAT(cs) (0x38 +
(cs *<br>
>> RAMIPS_SPI_DEV_OFFSET))<br>
>> -+#define RAMIPS_SPI_ARBITER 0xF0<br>
>> -<br>
>> - /* SPISTAT register bit field */<br>
>> - #define SPISTAT_BUSY BIT(0)<br>
>> -@@ -63,6 +69,19 @@<br>
>> - /* SPIFIFOSTAT register bit field */<br>
>> - #define SPIFIFOSTAT_TXFULL BIT(17)<br>
>> -<br>
>> -+#define SPICTL_ARB_EN BIT(31)<br>
>> -+#define SPI1_POR BIT(1)<br>
>> -+#define SPI0_POR BIT(0)<br>
>> -+<br>
>> -+#define RT2880_SPI_MODE_BITS (SPI_CPOL |
SPI_CPHA | SPI_LSB_FIRST<br>
>> | SPI_CS_HIGH)<br>
>> -+<br>
>> -+struct rt2880_spi;<br>
>> -+<br>
>> -+struct rt2880_spi_ops {<br>
>> -+ void (*init_hw)(struct rt2880_spi *rs);<br>
>> -+ int num_cs;<br>
>> -+};<br>
>> -+<br>
>> - struct rt2880_spi {<br>
>> - struct spi_master *master;<br>
>> - void __iomem *base;<br>
>> -@@ -70,6 +89,8 @@ struct rt2880_spi {<br>
>> - unsigned int speed;<br>
>> - struct clk *clk;<br>
>> - spinlock_t lock;<br>
>> -+<br>
>> -+ struct rt2880_spi_ops *ops;<br>
>> - };<br>
>> -<br>
>> - static inline struct rt2880_spi
*spidev_to_rt2880_spi(struct<br>
>> spi_device *spi)<br>
>> -@@ -115,6 +136,7 @@ static inline void
rt2880_spi_clrbits(st<br>
>> -<br>
>> - static int rt2880_spi_baudrate_set(struct
spi_device *spi, unsigned<br>
>> int speed)<br>
>> - {<br>
>> -+ int cs = spi->chip_select;<br>
>> - struct rt2880_spi *rs =
spidev_to_rt2880_spi(spi);<br>
>> - u32 rate;<br>
>> - u32 prescale;<br>
>> -@@ -142,9 +164,9 @@ static int
rt2880_spi_baudrate_set(struc<br>
>> - prescale = ilog2(rate / 2);<br>
>> - dev_dbg(&spi->dev,
"prescale:%u\n", prescale);<br>
>> -<br>
>> -- reg = rt2880_spi_read(rs,
RAMIPS_SPI_CFG);<br>
>> -+ reg = rt2880_spi_read(rs,
RAMIPS_SPI_CFG(cs));<br>
>> - reg = ((reg &
~SPICFG_SPICLK_PRESCALE_MASK) | prescale);<br>
>> -- rt2880_spi_write(rs, RAMIPS_SPI_CFG,
reg);<br>
>> -+ rt2880_spi_write(rs, RAMIPS_SPI_CFG(cs),
reg);<br>
>> - rs->speed = speed;<br>
>> - return 0;<br>
>> - }<br>
>> -@@ -157,7 +179,8 @@
rt2880_spi_setup_transfer(struct spi_dev<br>
>> - {<br>
>> - struct rt2880_spi *rs =
spidev_to_rt2880_spi(spi);<br>
>> - unsigned int speed =
spi->max_speed_hz;<br>
>> -- int rc;<br>
>> -+ int rc, cs = spi->chip_select;<br>
>> -+ u32 reg;<br>
>> -<br>
>> - if ((t != NULL) &&
t->speed_hz)<br>
>> - speed = t->speed_hz;<br>
>> -@@ -169,25 +192,68 @@
rt2880_spi_setup_transfer(struct spi_dev<br>
>> - return rc;<br>
>> - }<br>
>> -<br>
>> -+ reg = rt2880_spi_read(rs,
RAMIPS_SPI_CFG(cs));<br>
>> -+<br>
>> -+ reg = (reg & ~SPICFG_MSBFIRST);<br>
>> -+ if (!(spi->mode & SPI_LSB_FIRST))<br>
>> -+ reg |= SPICFG_MSBFIRST;<br>
>> -+<br>
>> -+ reg = (reg & ~(SPICFG_SPICLKPOL |
SPICFG_RXCLKEDGE_FALLING<br>
>> |SPICFG_TXCLKEDGE_FALLING));<br>
>> -+ switch(spi->mode & (SPI_CPOL |
SPI_CPHA)) {<br>
>> -+ case SPI_MODE_0:<br>
>> -+ reg |= SPICFG_SPICLKPOL |
SPICFG_TXCLKEDGE_FALLING;<br>
>> -+ break;<br>
>> -+ case SPI_MODE_1:<br>
>> -+ reg |= SPICFG_SPICLKPOL |
SPICFG_RXCLKEDGE_FALLING;<br>
>> -+ break;<br>
>> -+ case SPI_MODE_2:<br>
>> -+ reg |= SPICFG_RXCLKEDGE_FALLING;<br>
>> -+ break;<br>
>> -+ case SPI_MODE_3:<br>
>> -+ reg |= SPICFG_TXCLKEDGE_FALLING;<br>
>> -+ break;<br>
>> -+ }<br>
>> -+<br>
>> -+ rt2880_spi_write(rs, RAMIPS_SPI_CFG(cs),
reg);<br>
>> -+<br>
>> -+ reg = SPICTL_ARB_EN;<br>
>> -+ if (spi->mode & SPI_CS_HIGH) {<br>
>> -+ switch(cs) {<br>
>> -+ case 0:<br>
>> -+ reg |= SPI0_POR;<br>
>> -+ break;<br>
>> -+ case 1:<br>
>> -+ reg |= SPI1_POR;<br>
>> -+ break;<br>
>> -+ }<br>
>> -+ }<br>
>> -+<br>
>> -+ rt2880_spi_write(rs, RAMIPS_SPI_ARBITER,
reg);<br>
>> -+<br>
>> - return 0;<br>
>> - }<br>
>> -<br>
>> --static void rt2880_spi_set_cs(struct
rt2880_spi *rs, int enable)<br>
>> -+static void rt2880_spi_set_cs(struct
spi_device *spi, int enable)<br>
>> - {<br>
>> -+ struct rt2880_spi *rs =
spidev_to_rt2880_spi(spi);<br>
>> -+ int cs = spi->chip_select;<br>
>> -+<br>
>> - if (enable)<br>
>> -- rt2880_spi_clrbits(rs,
RAMIPS_SPI_CTL, SPICTL_SPIENA);<br>
>> -+ rt2880_spi_clrbits(rs,
RAMIPS_SPI_CTL(cs), SPICTL_SPIENA);<br>
>> - else<br>
>> -- rt2880_spi_setbits(rs,
RAMIPS_SPI_CTL, SPICTL_SPIENA);<br>
>> -+ rt2880_spi_setbits(rs,
RAMIPS_SPI_CTL(cs), SPICTL_SPIENA);<br>
>> - }<br>
>> -<br>
>> --static inline int
rt2880_spi_wait_till_ready(struct rt2880_spi *rs)<br>
>> -+static inline int
rt2880_spi_wait_till_ready(struct spi_device *spi)<br>
>> - {<br>
>> -+ struct rt2880_spi *rs =
spidev_to_rt2880_spi(spi);<br>
>> -+ int cs = spi->chip_select;<br>
>> - int i;<br>
>> -<br>
>> - for (i = 0; i <
RALINK_SPI_WAIT_MAX_LOOP; i++) {<br>
>> - u32 status;<br>
>> -<br>
>> -- status = rt2880_spi_read(rs,
RAMIPS_SPI_STAT);<br>
>> -+ status = rt2880_spi_read(rs,
RAMIPS_SPI_STAT(cs));<br>
>> - if ((status & SPISTAT_BUSY) == 0)<br>
>> - return 0;<br>
>> -<br>
>> -@@ -199,9 +265,10 @@ static inline int
rt2880_spi_wait_till_r<br>
>> - }<br>
>> -<br>
>> - static unsigned int<br>
>> --rt2880_spi_write_read(struct spi_device *spi,
struct spi_transfer<br>
>> *xfer)<br>
>> -+rt2880_spi_write_read(struct spi_device *spi,
struct list_head<br>
>> *list, struct spi_transfer *xfer)<br>
>> - {<br>
>> - struct rt2880_spi *rs =
spidev_to_rt2880_spi(spi);<br>
>> -+ int cs = spi->chip_select;<br>
>> - unsigned count = 0;<br>
>> - u8 *rx = xfer->rx_buf;<br>
>> - const u8 *tx = xfer->tx_buf;<br>
>> -@@ -213,9 +280,9 @@
rt2880_spi_write_read(struct spi_device<br>
>> -<br>
>> - if (tx) {<br>
>> - for (count = 0; count <
xfer->len; count++) {<br>
>> -- rt2880_spi_write(rs,
RAMIPS_SPI_DATA, tx[count]);<br>
>> -- rt2880_spi_setbits(rs,
RAMIPS_SPI_CTL, SPICTL_STARTWR);<br>
>> -- err =
rt2880_spi_wait_till_ready(rs);<br>
>> -+ rt2880_spi_write(rs,
RAMIPS_SPI_DATA(cs), tx[count]);<br>
>> -+ rt2880_spi_setbits(rs,
RAMIPS_SPI_CTL(cs), SPICTL_STARTWR);<br>
>> -+ err =
rt2880_spi_wait_till_ready(spi);<br>
>> - if (err) {<br>
>> - dev_err(&spi->dev, "TX
failed, err=%d\n", err);<br>
>> - goto out;<br>
>> -@@ -225,13 +292,13 @@
rt2880_spi_write_read(struct spi_device<br>
>> -<br>
>> - if (rx) {<br>
>> - for (count = 0; count <
xfer->len; count++) {<br>
>> -- rt2880_spi_setbits(rs,
RAMIPS_SPI_CTL, SPICTL_STARTRD);<br>
>> -- err =
rt2880_spi_wait_till_ready(rs);<br>
>> -+ rt2880_spi_setbits(rs,
RAMIPS_SPI_CTL(cs), SPICTL_STARTRD);<br>
>> -+ err =
rt2880_spi_wait_till_ready(spi);<br>
>> - if (err) {<br>
>> - dev_err(&spi->dev, "RX
failed, err=%d\n", err);<br>
>> - goto out;<br>
>> - }<br>
>> -- rx[count] = (u8)
rt2880_spi_read(rs, RAMIPS_SPI_DATA);<br>
>> -+ rx[count] = (u8)
rt2880_spi_read(rs, RAMIPS_SPI_DATA(cs));<br>
>> - }<br>
>> - }<br>
>> -<br>
>> -@@ -280,25 +347,25 @@ static int
rt2880_spi_transfer_one_messa<br>
>> - }<br>
>> -<br>
>> - if (!cs_active) {<br>
>> -- rt2880_spi_set_cs(rs, 1);<br>
>> -+ rt2880_spi_set_cs(spi, 1);<br>
>> - cs_active = 1;<br>
>> - }<br>
>> -<br>
>> - if (t->len)<br>
>> -- m->actual_length +=
rt2880_spi_write_read(spi, t);<br>
>> -+ m->actual_length +=
rt2880_spi_write_read(spi,<br>
>> &m->transfers, t);<br>
>> -<br>
>> - if (t->delay_usecs)<br>
>> - udelay(t->delay_usecs);<br>
>> -<br>
>> - if (t->cs_change) {<br>
>> -- rt2880_spi_set_cs(rs, 0);<br>
>> -+ rt2880_spi_set_cs(spi, 0);<br>
>> - cs_active = 0;<br>
>> - }<br>
>> - }<br>
>> -<br>
>> - msg_done:<br>
>> - if (cs_active)<br>
>> -- rt2880_spi_set_cs(rs, 0);<br>
>> -+ rt2880_spi_set_cs(spi, 0);<br>
>> -<br>
>> - m->status = status;<br>
>> - spi_finalize_current_message(master);<br>
>> -@@ -311,7 +378,7 @@ static int
rt2880_spi_setup(struct spi_d<br>
>> - struct rt2880_spi *rs =
spidev_to_rt2880_spi(spi);<br>
>> -<br>
>> - if ((spi->max_speed_hz == 0) ||<br>
>> -- (spi->max_speed_hz >
(rs->sys_freq / 2)))<br>
>> -+ (spi->max_speed_hz >
(rs->sys_freq / 2)))<br>
>> - spi->max_speed_hz =
(rs->sys_freq / 2);<br>
>> -<br>
>> - if (spi->max_speed_hz <
(rs->sys_freq / 128)) {<br>
>> -@@ -328,14 +395,47 @@ static int
rt2880_spi_setup(struct spi_d<br>
>> -<br>
>> - static void rt2880_spi_reset(struct
rt2880_spi *rs)<br>
>> - {<br>
>> -- rt2880_spi_write(rs, RAMIPS_SPI_CFG,<br>
>> -+ rt2880_spi_write(rs, RAMIPS_SPI_CFG(0),<br>
>> - SPICFG_MSBFIRST |
SPICFG_TXCLKEDGE_FALLING |<br>
>> - SPICFG_SPICLK_DIV16 |
SPICFG_SPICLKPOL);<br>
>> -- rt2880_spi_write(rs, RAMIPS_SPI_CTL,
SPICTL_HIZSDO |<br>
>> SPICTL_SPIENA);<br>
>> -+ rt2880_spi_write(rs, RAMIPS_SPI_CTL(0),
SPICTL_HIZSDO |<br>
>> SPICTL_SPIENA);<br>
>> - }<br>
>> -<br>
>> -+static void rt5350_spi_reset(struct
rt2880_spi *rs)<br>
>> -+{<br>
>> -+ int cs;<br>
>> -+<br>
>> -+ rt2880_spi_write(rs, RAMIPS_SPI_ARBITER,<br>
>> -+ SPICTL_ARB_EN);<br>
>> -+<br>
>> -+ for (cs = 0; cs <
rs->ops->num_cs; cs++) {<br>
>> -+ rt2880_spi_write(rs,
RAMIPS_SPI_CFG(cs),<br>
>> -+ SPICFG_MSBFIRST |
SPICFG_TXCLKEDGE_FALLING |<br>
>> -+ SPICFG_SPICLK_DIV16 |
SPICFG_SPICLKPOL);<br>
>> -+ rt2880_spi_write(rs,
RAMIPS_SPI_CTL(cs), SPICTL_HIZSDO |<br>
>> SPICTL_SPIENA);<br>
>> -+ }<br>
>> -+}<br>
>> -+<br>
>> -+static struct rt2880_spi_ops spi_ops[] = {<br>
>> -+ {<br>
>> -+ .init_hw = rt2880_spi_reset,<br>
>> -+ .num_cs = 1,<br>
>> -+ }, {<br>
>> -+ .init_hw = rt5350_spi_reset,<br>
>> -+ .num_cs = 2,<br>
>> -+ },<br>
>> -+};<br>
>> -+<br>
>> -+static const struct of_device_id
rt2880_spi_match[] = {<br>
>> -+ { .compatible = "ralink,rt2880-spi",
.data = &spi_ops[0]},<br>
>> -+ { .compatible = "ralink,rt5350-spi",
.data = &spi_ops[1]},<br>
>> -+ {},<br>
>> -+};<br>
>> -+MODULE_DEVICE_TABLE(of, rt2880_spi_match);<br>
>> -+<br>
>> - static int rt2880_spi_probe(struct
platform_device *pdev)<br>
>> - {<br>
>> -+ const struct of_device_id *match;<br>
>> - struct spi_master *master;<br>
>> - struct rt2880_spi *rs;<br>
>> - unsigned long flags;<br>
>> -@@ -343,6 +443,12 @@ static int
rt2880_spi_probe(struct platf<br>
>> - struct resource *r;<br>
>> - int status = 0;<br>
>> - struct clk *clk;<br>
>> -+ struct rt2880_spi_ops *ops;<br>
>> -+<br>
>> -+ match = of_match_device(rt2880_spi_match,
&pdev->dev);<br>
>> -+ if (!match)<br>
>> -+ return -EINVAL;<br>
>> -+ ops = (struct rt2880_spi_ops
*)match->data;<br>
>> -<br>
>> - r = platform_get_resource(pdev,
IORESOURCE_MEM, 0);<br>
>> - base =
devm_ioremap_resource(&pdev->dev, r);<br>
>> -@@ -366,14 +472,13 @@ static int
rt2880_spi_probe(struct platf<br>
>> - return -ENOMEM;<br>
>> - }<br>
>> -<br>
>> -- /* we support only mode 0, and no options
*/<br>
>> -- master->mode_bits = 0;<br>
>> -+ master->mode_bits =
RT2880_SPI_MODE_BITS;<br>
>> -<br>
>> - master->setup = rt2880_spi_setup;<br>
>> - master->transfer_one_message =
rt2880_spi_transfer_one_message;<br>
>> -- master->num_chipselect =
RALINK_NUM_CHIPSELECTS;<br>
>> - master->bits_per_word_mask =
SPI_BPW_MASK(8);<br>
>> - master->dev.of_node =
pdev->dev.of_node;<br>
>> -+ master->num_chipselect =
ops->num_cs;<br>
>> -<br>
>> - dev_set_drvdata(&pdev->dev,
master);<br>
>> -<br>
>> -@@ -382,12 +487,13 @@ static int
rt2880_spi_probe(struct platf<br>
>> - rs->clk = clk;<br>
>> - rs->master = master;<br>
>> - rs->sys_freq =
clk_get_rate(rs->clk);<br>
>> -+ rs->ops = ops;<br>
>> - dev_dbg(&pdev->dev, "sys_freq:
%u\n", rs->sys_freq);<br>
>> - spin_lock_irqsave(&rs->lock,
flags);<br>
>> -<br>
>> - device_reset(&pdev->dev);<br>
>> -<br>
>> -- rt2880_spi_reset(rs);<br>
>> -+ rs->ops->init_hw(rs);<br>
>> -<br>
>> - return spi_register_master(master);<br>
>> - }<br>
>> -@@ -408,12 +514,6 @@ static int
rt2880_spi_remove(struct plat<br>
>> -<br>
>> - MODULE_ALIAS("platform:" DRIVER_NAME);<br>
>> -<br>
>> --static const struct of_device_id
rt2880_spi_match[] = {<br>
>> -- { .compatible = "ralink,rt2880-spi" },<br>
>> -- {},<br>
>> --};<br>
>> --MODULE_DEVICE_TABLE(of, rt2880_spi_match);<br>
>> --<br>
>> - static struct platform_driver
rt2880_spi_driver = {<br>
>> - .driver = {<br>
>> - .name = DRIVER_NAME,<br>
</div>
</div>
</blockquote>
</div>
<br>
</div>
</blockquote>
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