<p dir="ltr">Hallo,</p>
<p dir="ltr">if you mean "CONFIG_OF_MDIO"? I have added this define because if we have no "openfirmware" a dummy function will be called. Or do you mean the whole patch?</p>
<p dir="ltr">Regards</p>
<p dir="ltr">Flo<br></p>
<p dir="ltr">Am 21.11.2015 6:55 nachm. schrieb "John Crispin" <<a href="mailto:blogic@openwrt.org">blogic@openwrt.org</a>>:<br>
><br>
> Hi<br>
><br>
> 1 comment inline<br>
><br>
> On 09/11/2015 13:44, Florian Eckert wrote:<br>
> > This patch adds the posibility to config the led behaviour of the lantiq phys<br>
> > over the devicetree bindings.It patches the 0023-NET-PHY-adds-driver-for-lantiq-PHY11G<br>
> > for 3.18 and 4.1. I have also added a register description overview for<br>
> > applicable values. This goes to the documentation folder in the linux kernel.<br>
> ><br>
> > Signed-off-by: Florian Eckert <<a href="mailto:Eckert.Florian@googlemail.com">Eckert.Florian@googlemail.com</a>><br>
> > ---<br>
> ><br>
> > v2 add Signed-off-by marker<br>
> ><br>
> > ...023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch | 268 ++++++++++++++++++++-<br>
> > ...023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch | 268 ++++++++++++++++++++-<br>
> > 2 files changed, 534 insertions(+), 2 deletions(-)<br>
> > mode change 100644 => 100755 target/linux/lantiq/patches-3.18/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch<br>
> ><br>
> > diff --git a/target/linux/lantiq/patches-3.18/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch b/target/linux/lantiq/patches-3.18/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch<br>
> > old mode 100644<br>
> > new mode 100755<br>
> > index 6d1805f..55db4c7<br>
> > --- a/target/linux/lantiq/patches-3.18/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch<br>
> > +++ b/target/linux/lantiq/patches-3.18/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch<br>
> > @@ -37,7 +37,7 @@ Signed-off-by: John Crispin <<a href="mailto:blogic@openwrt.org">blogic@openwrt.org</a>><br>
> > obj-$(CONFIG_AT803X_PHY) += at803x.o<br>
> > --- /dev/null<br>
> > +++ b/drivers/net/phy/lantiq.c<br>
> > -@@ -0,0 +1,231 @@<br>
> > +@@ -0,0 +1,278 @@<br>
> > +/*<br>
> > + * This program is free software; you can redistribute it and/or modify<br>
> > + * it under the terms of the GNU General Public License as published by<br>
> > @@ -58,6 +58,7 @@ Signed-off-by: John Crispin <<a href="mailto:blogic@openwrt.org">blogic@openwrt.org</a>><br>
> > +<br>
> > +#include <linux/module.h><br>
> > +#include <linux/phy.h><br>
> > ++#include <linux/of.h><br>
> > +<br>
> > +#define MII_MMDCTRL 0x0d<br>
> > +#define MII_MMDDATA 0x0e<br>
> > @@ -104,6 +105,50 @@ Signed-off-by: John Crispin <<a href="mailto:blogic@openwrt.org">blogic@openwrt.org</a>><br>
> > + return 0;<br>
> > +}<br>
> > +<br>
> > ++#if IS_ENABLED(CONFIG_OF_MDIO)<br>
><br>
> we are inside a phy driver here that we talk to using a mdio bus. are<br>
> you sure this is required ?<br>
><br>
> John<br>
><br>
> > ++static int vr9_gphy_of_reg_init(struct phy_device *phydev)<br>
> > ++{<br>
> > ++ u32 tmp;<br>
> > ++<br>
> > ++ /* store the led values if one was passed by the devicetree */<br>
> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,ledch", &tmp))<br>
> > ++ vr9_gphy_mmd_write(phydev, 0x1e0, tmp);<br>
> > ++<br>
> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,ledcl", &tmp))<br>
> > ++ vr9_gphy_mmd_write(phydev, 0x1e1, tmp);<br>
> > ++<br>
> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led0h", &tmp))<br>
> > ++ vr9_gphy_mmd_write(phydev, 0x1e2, tmp);<br>
> > ++<br>
> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led0l", &tmp))<br>
> > ++ vr9_gphy_mmd_write(phydev, 0x1e3, tmp);<br>
> > ++<br>
> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led1h", &tmp))<br>
> > ++ vr9_gphy_mmd_write(phydev, 0x1e4, tmp);<br>
> > ++<br>
> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led1l", &tmp))<br>
> > ++ vr9_gphy_mmd_write(phydev, 0x1e5, tmp);<br>
> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led2h", &tmp))<br>
> > ++ vr9_gphy_mmd_write(phydev, 0x1e6, tmp);<br>
> > ++<br>
> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led2l", &tmp))<br>
> > ++ vr9_gphy_mmd_write(phydev, 0x1e7, tmp);<br>
> > ++<br>
> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led3h", &tmp))<br>
> > ++ vr9_gphy_mmd_write(phydev, 0x1e8, tmp);<br>
> > ++<br>
> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led3l", &tmp))<br>
> > ++ vr9_gphy_mmd_write(phydev, 0x1e9, tmp);<br>
> > ++<br>
> > ++ return 0;<br>
> > ++}<br>
> > ++#else<br>
> > ++static int vr9_gphy_of_reg_init(struct phy_device *phydev)<br>
> > ++{<br>
> > ++ return 0;<br>
> > ++}<br>
> > ++#endif /* CONFIG_OF_MDIO */<br>
> > ++<br>
> > +static int vr9_gphy_config_init(struct phy_device *phydev)<br>
> > +{<br>
> > + int err;<br>
> > @@ -129,6 +174,8 @@ Signed-off-by: John Crispin <<a href="mailto:blogic@openwrt.org">blogic@openwrt.org</a>><br>
> > + vr9_gphy_mmd_write(phydev, 0x1e8, 0x40);<br>
> > + vr9_gphy_mmd_write(phydev, 0x1e9, 0x20);<br>
> > +<br>
> > ++ vr9_gphy_of_reg_init(phydev);<br>
> > ++<br>
> > + return 0;<br>
> > +}<br>
> > +<br>
> > @@ -269,3 +316,222 @@ Signed-off-by: John Crispin <<a href="mailto:blogic@openwrt.org">blogic@openwrt.org</a>><br>
> > +MODULE_DESCRIPTION("Lantiq PHY drivers");<br>
> > +MODULE_AUTHOR("Daniel Schwierzeck <<a href="mailto:daniel.schwierzeck@googlemail.com">daniel.schwierzeck@googlemail.com</a>>");<br>
> > +MODULE_LICENSE("GPL");<br>
> > +--- /dev/null<br>
> > ++++ b/Documentation/devicetree/bindings/phy/phy-lanitq.txt<br>
> > +@@ -0,0 +1,216 @@<br>
> > ++Lanitq PHY binding<br>
> > ++============================================<br>
> > ++<br>
> > ++This devicetree binding controls the lantiq ethernet phys led functionality.<br>
> > ++<br>
> > ++Example:<br>
> > ++ mdio@0 {<br>
> > ++ #address-cells = <1>;<br>
> > ++ #size-cells = <0>;<br>
> > ++ compatible = "lantiq,xrx200-mdio";<br>
> > ++ phy5: ethernet-phy@5 {<br>
> > ++ reg = <0x1>;<br>
> > ++ compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";<br>
> > ++ };<br>
> > ++ phy11: ethernet-phy@11 {<br>
> > ++ reg = <0x11>;<br>
> > ++ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";<br>
> > ++ lantiq,led2h = <0x00>;<br>
> > ++ lantiq,led2l = <0x03>;<br>
> > ++ };<br>
> > ++ phy12: ethernet-phy@12 {<br>
> > ++ reg = <0x12>;<br>
> > ++ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";<br>
> > ++ lantiq,led1h = <0x00>;<br>
> > ++ lantiq,led1l = <0x03>;<br>
> > ++ };<br>
> > ++ phy13: ethernet-phy@13 {<br>
> > ++ reg = <0x13>;<br>
> > ++ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";<br>
> > ++ lantiq,led2h = <0x00>;<br>
> > ++ lantiq,led2l = <0x03>;<br>
> > ++ };<br>
> > ++ phy14: ethernet-phy@14 {<br>
> > ++ reg = <0x14>;<br>
> > ++ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";<br>
> > ++ lantiq,led1h = <0x00>;<br>
> > ++ lantiq,led1l = <0x03>;<br>
> > ++ };<br>
> > ++ };<br>
> > ++<br>
> > ++Register Description<br>
> > ++============================================<br>
> > ++<br>
> > ++LEDCH:<br>
> > ++<br>
> > ++Name Hardware Reset Value<br>
> > ++LEDCH 0x00C5<br>
> > ++<br>
> > ++| 15 | | | | | | | 8 |<br>
> > ++=========================================<br>
> > ++| RES |<br>
> > ++=========================================<br>
> > ++<br>
> > ++| 7 | | | | | | | 0 |<br>
> > ++=========================================<br>
> > ++| FBF | SBF |RES | NACS |<br>
> > ++=========================================<br>
> > ++<br>
> > ++Field Bits Type Description<br>
> > ++FBC 7:6 RW Fast Blink Frequency<br>
> > ++ ---<br>
> > ++ 0x0 (00b) F02HZ 2 Hz blinking frequency<br>
> > ++ 0x1 (01b) F04HZ 4 Hz blinking frequency<br>
> > ++ 0x2 (10b) F08HZ 8 Hz blinking frequency<br>
> > ++ 0x3 (11b) F16HZ 16 Hz blinking frequency<br>
> > ++<br>
> > ++SBF 5:4 RW Slow Blink Frequency<br>
> > ++ ---<br>
> > ++ 0x0 (00b) F02HZ 2 Hz blinking frequency<br>
> > ++ 0x1 (01b) F04HZ 4 Hz blinking frequency<br>
> > ++ 0x2 (10b) F08HZ 8 Hz blinking frequency<br>
> > ++ 0x3 (11b) F16HZ 16 Hz blinking frequency<br>
> > ++<br>
> > ++NACS 2:0 RW Inverse of Scan Function<br>
> > ++ ---<br>
> > ++ 0x0 (000b) NONE No Function<br>
> > ++ 0x1 (001b) LINK Complex function enabled when link is up<br>
> > ++ 0x2 (010b) PDOWN Complex function enabled when device is powered-down<br>
> > ++ 0x3 (011b) EEE Complex function enabled when device is in EEE mode<br>
> > ++ 0x4 (100b) ANEG Complex function enabled when auto-negotiation is running<br>
> > ++ 0x5 (101b) ABIST Complex function enabled when analog self-test is running<br>
> > ++ 0x6 (110b) CDIAG Complex function enabled when cable diagnostics are running<br>
> > ++ 0x7 (111b) TEST Complex function enabled when test mode is running<br>
> > ++<br>
> > ++LEDCL:<br>
> > ++<br>
> > ++Name Hardware Reset Value<br>
> > ++LEDCL 0x0067<br>
> > ++<br>
> > ++| 15 | | | | | | | 8 |<br>
> > ++=========================================<br>
> > ++| RES |<br>
> > ++=========================================<br>
> > ++<br>
> > ++| 7 | | | | | | | 0 |<br>
> > ++=========================================<br>
> > ++|RES | SCAN |RES | CBLINK |<br>
> > ++=========================================<br>
> > ++<br>
> > ++Field Bits Type Description<br>
> > ++SCAN 6:4 RW Complex Scan Configuration<br>
> > ++ ---<br>
> > ++ 000 B NONE No Function<br>
> > ++ 001 B LINK Complex function enabled when link is up<br>
> > ++ 010 B PDOWN Complex function enabled when device is powered-down<br>
> > ++ 011 B EEE Complex function enabled when device is in EEE mode<br>
> > ++ 100 B ANEG Complex function enabled when auto-negotiation is running<br>
> > ++ 101 B ABIST Complex function enabled when analog self-test is running<br>
> > ++ 110 B CDIAG Complex function enabled when cable diagnostics are running<br>
> > ++ 111 B TEST Complex function enabled when test mode is running<br>
> > ++<br>
> > ++CBLINK 2:0 RW Complex Blinking Configuration<br>
> > ++ ---<br>
> > ++ 000 B NONE No Function<br>
> > ++ 001 B LINK Complex function enabled when link is up<br>
> > ++ 010 B PDOWN Complex function enabled when device is powered-down<br>
> > ++ 011 B EEE Complex function enabled when device is in EEE mode<br>
> > ++ 100 B ANEG Complex function enabled when auto-negotiation is running<br>
> > ++ 101 B ABIST Complex function enabled when analog self-test is running<br>
> > ++ 110 B CDIAG Complex function enabled when cable diagnostics are running<br>
> > ++ 111 B TEST Complex function enabled when test mode is running<br>
> > ++<br>
> > ++LEDxH:<br>
> > ++<br>
> > ++Name Hardware Reset Value<br>
> > ++LED0H 0x0070<br>
> > ++LED1H 0x0020<br>
> > ++LED2H 0x0040<br>
> > ++LED3H 0x0040<br>
> > ++<br>
> > ++| 15 | | | | | | | 8 |<br>
> > ++=========================================<br>
> > ++| RES |<br>
> > ++=========================================<br>
> > ++<br>
> > ++| 7 | | | | | | | 0 |<br>
> > ++=========================================<br>
> > ++| CON | BLINKF |<br>
> > ++=========================================<br>
> > ++<br>
> > ++Field Bits Type Description<br>
> > ++CON 7:4 RW Constant On Configuration<br>
> > ++ ---<br>
> > ++ 0x0 (0000b) NONE LED does not light up constantly<br>
> > ++ 0x1 (0001b) LINK10 LED is on when link is 10 Mbit/s<br>
> > ++ 0x2 (0010b) LINK100 LED is on when link is 100 Mbit/s<br>
> > ++ 0x3 (0011b) LINK10X LED is on when link is 10/100 Mbit/s<br>
> > ++ 0x4 (0100b) LINK1000 LED is on when link is 1000 Mbit/s<br>
> > ++ 0x5 (0101b) LINK10_0 LED is on when link is 10/1000 Mbit/s<br>
> > ++ 0x6 (0110b) LINK100X LED is on when link is 100/1000 Mbit/s<br>
> > ++ 0x7 (0111b) LINK10XX LED is on when link is 10/100/1000 Mbit/s<br>
> > ++ 0x8 (1000b) PDOWN LED is on when device is powered-down<br>
> > ++ 0x9 (1001b) EEE LED is on when device is in EEE mode<br>
> > ++ 0xA (1010b) ANEG LED is on when auto-negotiation is running<br>
> > ++ 0xB (1011b) ABIST LED is on when analog self-test is running<br>
> > ++ 0xC (1100b) CDIAG LED is on when cable diagnostics are running<br>
> > ++<br>
> > ++BLINKF 3:0 RW Fast Blinking Configuration<br>
> > ++ ---<br>
> > ++ 0x0 (0000b) NONE No Blinking<br>
> > ++ 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s<br>
> > ++ 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s<br>
> > ++ 0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s<br>
> > ++ 0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s<br>
> > ++ 0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s<br>
> > ++ 0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s<br>
> > ++ 0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s<br>
> > ++ 0x8 (1000b) PDOWN Blink when device is powered-down<br>
> > ++ 0x9 (1001b) EEE Blink when device is in EEE mode<br>
> > ++ 0xA (1010b) ANEG Blink when auto-negotiation is running<br>
> > ++ 0xB (1011b) ABIST Blink when analog self-test is running<br>
> > ++ 0xC (1100b) CDIAG Blink when cable diagnostics are running<br>
> > ++<br>
> > ++LEDxL:<br>
> > ++<br>
> > ++Name Hardware Reset Value<br>
> > ++LED0L 0x0003<br>
> > ++LED1L 0x0000<br>
> > ++LED2L 0x0000<br>
> > ++LED3L 0x0020<br>
> > ++<br>
> > ++| 15 | | | | | | | 8 |<br>
> > ++=========================================<br>
> > ++| RES |<br>
> > ++=========================================<br>
> > ++<br>
> > ++| 7 | | | | | | | 0 |<br>
> > ++=========================================<br>
> > ++| BLINKS | PULSE |<br>
> > ++=========================================<br>
> > ++<br>
> > ++Field Bits Type Description<br>
> > ++BLINKS 7:4 RW Slow Blinkin Configuration<br>
> > ++ ---<br>
> > ++ 0x0 (0000b) NONE No Blinking<br>
> > ++ 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s<br>
> > ++ 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s<br>
> > ++ 0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s<br>
> > ++ 0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s<br>
> > ++ 0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s<br>
> > ++ 0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s<br>
> > ++ 0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s<br>
> > ++ 0x8 (1000b) PDOWN Blink when device is powered-down<br>
> > ++ 0x9 (1001b) EEE Blink when device is in EEE mode<br>
> > ++ 0xA (1010b) ANEG Blink when auto-negotiation is running<br>
> > ++ 0xB (1011b) ABIST Blink when analog self-test is running<br>
> > ++ 0xC (1100b) CDIAG Blink when cable diagnostics are runningning<br>
> > ++<br>
> > ++PULSE 3:0 RW Pulsing Configuration<br>
> > ++ The pulse field is a mask field by which certain events can be combined<br>
> > ++ ---<br>
> > ++ 0x0 (0000b) NONE No pulsing<br>
> > ++ 0x1 (0001b) TXACT Transmit activity<br>
> > ++ 0x2 (0010b) RXACT Receive activity<br>
> > ++ 0x4 (0100b) COL Collision<br>
> > ++ 0x8 (1000b) RES Reserved<br>
> > diff --git a/target/linux/lantiq/patches-4.1/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch b/target/linux/lantiq/patches-4.1/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch<br>
> > index 08e6b64..3f50a3b 100644<br>
> > --- a/target/linux/lantiq/patches-4.1/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch<br>
> > +++ b/target/linux/lantiq/patches-4.1/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch<br>
> > @@ -37,7 +37,7 @@ Signed-off-by: John Crispin <<a href="mailto:blogic@openwrt.org">blogic@openwrt.org</a>><br>
> > obj-$(CONFIG_AT803X_PHY) += at803x.o<br>
> > --- /dev/null<br>
> > +++ b/drivers/net/phy/lantiq.c<br>
> > -@@ -0,0 +1,231 @@<br>
> > +@@ -0,0 +1,278 @@<br>
> > +/*<br>
> > + * This program is free software; you can redistribute it and/or modify<br>
> > + * it under the terms of the GNU General Public License as published by<br>
> > @@ -58,6 +58,7 @@ Signed-off-by: John Crispin <<a href="mailto:blogic@openwrt.org">blogic@openwrt.org</a>><br>
> > +<br>
> > +#include <linux/module.h><br>
> > +#include <linux/phy.h><br>
> > ++#include <linux/of.h><br>
> > +<br>
> > +#define MII_MMDCTRL 0x0d<br>
> > +#define MII_MMDDATA 0x0e<br>
> > @@ -104,6 +105,50 @@ Signed-off-by: John Crispin <<a href="mailto:blogic@openwrt.org">blogic@openwrt.org</a>><br>
> > + return 0;<br>
> > +}<br>
> > +<br>
> > ++#if IS_ENABLED(CONFIG_OF_MDIO)<br>
> > ++static int vr9_gphy_of_reg_init(struct phy_device *phydev)<br>
> > ++{<br>
> > ++ u32 tmp;<br>
> > ++<br>
> > ++ /* store the led values if one was passed by the devicetree */<br>
> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,ledch", &tmp))<br>
> > ++ vr9_gphy_mmd_write(phydev, 0x1e0, tmp);<br>
> > ++<br>
> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,ledcl", &tmp))<br>
> > ++ vr9_gphy_mmd_write(phydev, 0x1e1, tmp);<br>
> > ++<br>
> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led0h", &tmp))<br>
> > ++ vr9_gphy_mmd_write(phydev, 0x1e2, tmp);<br>
> > ++<br>
> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led0l", &tmp))<br>
> > ++ vr9_gphy_mmd_write(phydev, 0x1e3, tmp);<br>
> > ++<br>
> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led1h", &tmp))<br>
> > ++ vr9_gphy_mmd_write(phydev, 0x1e4, tmp);<br>
> > ++<br>
> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led1l", &tmp))<br>
> > ++ vr9_gphy_mmd_write(phydev, 0x1e5, tmp);<br>
> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led2h", &tmp))<br>
> > ++ vr9_gphy_mmd_write(phydev, 0x1e6, tmp);<br>
> > ++<br>
> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led2l", &tmp))<br>
> > ++ vr9_gphy_mmd_write(phydev, 0x1e7, tmp);<br>
> > ++<br>
> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led3h", &tmp))<br>
> > ++ vr9_gphy_mmd_write(phydev, 0x1e8, tmp);<br>
> > ++<br>
> > ++ if (!of_property_read_u32(phydev->dev.of_node, "lantiq,led3l", &tmp))<br>
> > ++ vr9_gphy_mmd_write(phydev, 0x1e9, tmp);<br>
> > ++<br>
> > ++ return 0;<br>
> > ++}<br>
> > ++#else<br>
> > ++static int vr9_gphy_of_reg_init(struct phy_device *phydev)<br>
> > ++{<br>
> > ++ return 0;<br>
> > ++}<br>
> > ++#endif /* CONFIG_OF_MDIO */<br>
> > ++<br>
> > +static int vr9_gphy_config_init(struct phy_device *phydev)<br>
> > +{<br>
> > + int err;<br>
> > @@ -129,6 +174,8 @@ Signed-off-by: John Crispin <<a href="mailto:blogic@openwrt.org">blogic@openwrt.org</a>><br>
> > + vr9_gphy_mmd_write(phydev, 0x1e8, 0x40);<br>
> > + vr9_gphy_mmd_write(phydev, 0x1e9, 0x20);<br>
> > +<br>
> > ++ vr9_gphy_of_reg_init(phydev);<br>
> > ++<br>
> > + return 0;<br>
> > +}<br>
> > +<br>
> > @@ -269,3 +316,222 @@ Signed-off-by: John Crispin <<a href="mailto:blogic@openwrt.org">blogic@openwrt.org</a>><br>
> > +MODULE_DESCRIPTION("Lantiq PHY drivers");<br>
> > +MODULE_AUTHOR("Daniel Schwierzeck <<a href="mailto:daniel.schwierzeck@googlemail.com">daniel.schwierzeck@googlemail.com</a>>");<br>
> > +MODULE_LICENSE("GPL");<br>
> > +--- /dev/null<br>
> > ++++ b/Documentation/devicetree/bindings/phy/phy-lanitq.txt<br>
> > +@@ -0,0 +1,216 @@<br>
> > ++Lanitq PHY binding<br>
> > ++============================================<br>
> > ++<br>
> > ++This devicetree binding controls the lantiq ethernet phys led functionality.<br>
> > ++<br>
> > ++Example:<br>
> > ++ mdio@0 {<br>
> > ++ #address-cells = <1>;<br>
> > ++ #size-cells = <0>;<br>
> > ++ compatible = "lantiq,xrx200-mdio";<br>
> > ++ phy5: ethernet-phy@5 {<br>
> > ++ reg = <0x1>;<br>
> > ++ compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";<br>
> > ++ };<br>
> > ++ phy11: ethernet-phy@11 {<br>
> > ++ reg = <0x11>;<br>
> > ++ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";<br>
> > ++ lantiq,led2h = <0x00>;<br>
> > ++ lantiq,led2l = <0x03>;<br>
> > ++ };<br>
> > ++ phy12: ethernet-phy@12 {<br>
> > ++ reg = <0x12>;<br>
> > ++ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";<br>
> > ++ lantiq,led1h = <0x00>;<br>
> > ++ lantiq,led1l = <0x03>;<br>
> > ++ };<br>
> > ++ phy13: ethernet-phy@13 {<br>
> > ++ reg = <0x13>;<br>
> > ++ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";<br>
> > ++ lantiq,led2h = <0x00>;<br>
> > ++ lantiq,led2l = <0x03>;<br>
> > ++ };<br>
> > ++ phy14: ethernet-phy@14 {<br>
> > ++ reg = <0x14>;<br>
> > ++ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";<br>
> > ++ lantiq,led1h = <0x00>;<br>
> > ++ lantiq,led1l = <0x03>;<br>
> > ++ };<br>
> > ++ };<br>
> > ++<br>
> > ++Register Description<br>
> > ++============================================<br>
> > ++<br>
> > ++LEDCH:<br>
> > ++<br>
> > ++Name Hardware Reset Value<br>
> > ++LEDCH 0x00C5<br>
> > ++<br>
> > ++| 15 | | | | | | | 8 |<br>
> > ++=========================================<br>
> > ++| RES |<br>
> > ++=========================================<br>
> > ++<br>
> > ++| 7 | | | | | | | 0 |<br>
> > ++=========================================<br>
> > ++| FBF | SBF |RES | NACS |<br>
> > ++=========================================<br>
> > ++<br>
> > ++Field Bits Type Description<br>
> > ++FBC 7:6 RW Fast Blink Frequency<br>
> > ++ ---<br>
> > ++ 0x0 (00b) F02HZ 2 Hz blinking frequency<br>
> > ++ 0x1 (01b) F04HZ 4 Hz blinking frequency<br>
> > ++ 0x2 (10b) F08HZ 8 Hz blinking frequency<br>
> > ++ 0x3 (11b) F16HZ 16 Hz blinking frequency<br>
> > ++<br>
> > ++SBF 5:4 RW Slow Blink Frequency<br>
> > ++ ---<br>
> > ++ 0x0 (00b) F02HZ 2 Hz blinking frequency<br>
> > ++ 0x1 (01b) F04HZ 4 Hz blinking frequency<br>
> > ++ 0x2 (10b) F08HZ 8 Hz blinking frequency<br>
> > ++ 0x3 (11b) F16HZ 16 Hz blinking frequency<br>
> > ++<br>
> > ++NACS 2:0 RW Inverse of Scan Function<br>
> > ++ ---<br>
> > ++ 0x0 (000b) NONE No Function<br>
> > ++ 0x1 (001b) LINK Complex function enabled when link is up<br>
> > ++ 0x2 (010b) PDOWN Complex function enabled when device is powered-down<br>
> > ++ 0x3 (011b) EEE Complex function enabled when device is in EEE mode<br>
> > ++ 0x4 (100b) ANEG Complex function enabled when auto-negotiation is running<br>
> > ++ 0x5 (101b) ABIST Complex function enabled when analog self-test is running<br>
> > ++ 0x6 (110b) CDIAG Complex function enabled when cable diagnostics are running<br>
> > ++ 0x7 (111b) TEST Complex function enabled when test mode is running<br>
> > ++<br>
> > ++LEDCL:<br>
> > ++<br>
> > ++Name Hardware Reset Value<br>
> > ++LEDCL 0x0067<br>
> > ++<br>
> > ++| 15 | | | | | | | 8 |<br>
> > ++=========================================<br>
> > ++| RES |<br>
> > ++=========================================<br>
> > ++<br>
> > ++| 7 | | | | | | | 0 |<br>
> > ++=========================================<br>
> > ++|RES | SCAN |RES | CBLINK |<br>
> > ++=========================================<br>
> > ++<br>
> > ++Field Bits Type Description<br>
> > ++SCAN 6:4 RW Complex Scan Configuration<br>
> > ++ ---<br>
> > ++ 000 B NONE No Function<br>
> > ++ 001 B LINK Complex function enabled when link is up<br>
> > ++ 010 B PDOWN Complex function enabled when device is powered-down<br>
> > ++ 011 B EEE Complex function enabled when device is in EEE mode<br>
> > ++ 100 B ANEG Complex function enabled when auto-negotiation is running<br>
> > ++ 101 B ABIST Complex function enabled when analog self-test is running<br>
> > ++ 110 B CDIAG Complex function enabled when cable diagnostics are running<br>
> > ++ 111 B TEST Complex function enabled when test mode is running<br>
> > ++<br>
> > ++CBLINK 2:0 RW Complex Blinking Configuration<br>
> > ++ ---<br>
> > ++ 000 B NONE No Function<br>
> > ++ 001 B LINK Complex function enabled when link is up<br>
> > ++ 010 B PDOWN Complex function enabled when device is powered-down<br>
> > ++ 011 B EEE Complex function enabled when device is in EEE mode<br>
> > ++ 100 B ANEG Complex function enabled when auto-negotiation is running<br>
> > ++ 101 B ABIST Complex function enabled when analog self-test is running<br>
> > ++ 110 B CDIAG Complex function enabled when cable diagnostics are running<br>
> > ++ 111 B TEST Complex function enabled when test mode is running<br>
> > ++<br>
> > ++LEDxH:<br>
> > ++<br>
> > ++Name Hardware Reset Value<br>
> > ++LED0H 0x0070<br>
> > ++LED1H 0x0020<br>
> > ++LED2H 0x0040<br>
> > ++LED3H 0x0040<br>
> > ++<br>
> > ++| 15 | | | | | | | 8 |<br>
> > ++=========================================<br>
> > ++| RES |<br>
> > ++=========================================<br>
> > ++<br>
> > ++| 7 | | | | | | | 0 |<br>
> > ++=========================================<br>
> > ++| CON | BLINKF |<br>
> > ++=========================================<br>
> > ++<br>
> > ++Field Bits Type Description<br>
> > ++CON 7:4 RW Constant On Configuration<br>
> > ++ ---<br>
> > ++ 0x0 (0000b) NONE LED does not light up constantly<br>
> > ++ 0x1 (0001b) LINK10 LED is on when link is 10 Mbit/s<br>
> > ++ 0x2 (0010b) LINK100 LED is on when link is 100 Mbit/s<br>
> > ++ 0x3 (0011b) LINK10X LED is on when link is 10/100 Mbit/s<br>
> > ++ 0x4 (0100b) LINK1000 LED is on when link is 1000 Mbit/s<br>
> > ++ 0x5 (0101b) LINK10_0 LED is on when link is 10/1000 Mbit/s<br>
> > ++ 0x6 (0110b) LINK100X LED is on when link is 100/1000 Mbit/s<br>
> > ++ 0x7 (0111b) LINK10XX LED is on when link is 10/100/1000 Mbit/s<br>
> > ++ 0x8 (1000b) PDOWN LED is on when device is powered-down<br>
> > ++ 0x9 (1001b) EEE LED is on when device is in EEE mode<br>
> > ++ 0xA (1010b) ANEG LED is on when auto-negotiation is running<br>
> > ++ 0xB (1011b) ABIST LED is on when analog self-test is running<br>
> > ++ 0xC (1100b) CDIAG LED is on when cable diagnostics are running<br>
> > ++<br>
> > ++BLINKF 3:0 RW Fast Blinking Configuration<br>
> > ++ ---<br>
> > ++ 0x0 (0000b) NONE No Blinking<br>
> > ++ 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s<br>
> > ++ 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s<br>
> > ++ 0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s<br>
> > ++ 0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s<br>
> > ++ 0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s<br>
> > ++ 0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s<br>
> > ++ 0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s<br>
> > ++ 0x8 (1000b) PDOWN Blink when device is powered-down<br>
> > ++ 0x9 (1001b) EEE Blink when device is in EEE mode<br>
> > ++ 0xA (1010b) ANEG Blink when auto-negotiation is running<br>
> > ++ 0xB (1011b) ABIST Blink when analog self-test is running<br>
> > ++ 0xC (1100b) CDIAG Blink when cable diagnostics are running<br>
> > ++<br>
> > ++LEDxL:<br>
> > ++<br>
> > ++Name Hardware Reset Value<br>
> > ++LED0L 0x0003<br>
> > ++LED1L 0x0000<br>
> > ++LED2L 0x0000<br>
> > ++LED3L 0x0020<br>
> > ++<br>
> > ++| 15 | | | | | | | 8 |<br>
> > ++=========================================<br>
> > ++| RES |<br>
> > ++=========================================<br>
> > ++<br>
> > ++| 7 | | | | | | | 0 |<br>
> > ++=========================================<br>
> > ++| BLINKS | PULSE |<br>
> > ++=========================================<br>
> > ++<br>
> > ++Field Bits Type Description<br>
> > ++BLINKS 7:4 RW Slow Blinkin Configuration<br>
> > ++ ---<br>
> > ++ 0x0 (0000b) NONE No Blinking<br>
> > ++ 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s<br>
> > ++ 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s<br>
> > ++ 0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s<br>
> > ++ 0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s<br>
> > ++ 0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s<br>
> > ++ 0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s<br>
> > ++ 0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s<br>
> > ++ 0x8 (1000b) PDOWN Blink when device is powered-down<br>
> > ++ 0x9 (1001b) EEE Blink when device is in EEE mode<br>
> > ++ 0xA (1010b) ANEG Blink when auto-negotiation is running<br>
> > ++ 0xB (1011b) ABIST Blink when analog self-test is running<br>
> > ++ 0xC (1100b) CDIAG Blink when cable diagnostics are runningning<br>
> > ++<br>
> > ++PULSE 3:0 RW Pulsing Configuration<br>
> > ++ The pulse field is a mask field by which certain events can be combined<br>
> > ++ ---<br>
> > ++ 0x0 (0000b) NONE No pulsing<br>
> > ++ 0x1 (0001b) TXACT Transmit activity<br>
> > ++ 0x2 (0010b) RXACT Receive activity<br>
> > ++ 0x4 (0100b) COL Collision<br>
> > ++ 0x8 (1000b) RES Reserved<br>
> ><br>
</p>