<div dir="ltr"><div>according to mtk sdk 4300 at kernel version linux-2.6.36.x<br></div>at 40Mhz Xtal it use 20 not 40.<br><div><br>#elif defined (CONFIG_RALINK_MT7621)<br> case 0:<br> reg = (*(volatile u32 *)(RALINK_SYSCTL_BASE + 0x44));<br> cpu_fdiv = ((reg >> 8) & 0x1F);<br> cpu_ffrac = (reg & 0x1F);<br> mips_cpu_feq = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;<br> break;<br> case 1: //CPU PLL<br> reg = (*(volatile u32 *)(RALINK_MEMCTRL_BASE + 0x648));<br> fbdiv = ((reg >> 4) & 0x7F) + 1;<br> reg = (*(volatile u32 *)(RALINK_SYSCTL_BASE + 0x10));<br> reg = (reg >> 6) & 0x7;<br> if(reg >= 6) { //25Mhz Xtal<br> mips_cpu_feq = 25 * fbdiv * 1000 * 1000;<br> } else if(reg >=3) { //40Mhz Xtal<br> mips_cpu_feq = 20 * fbdiv * 1000 * 1000;<br> } else { // 20Mhz Xtal<br> /* TODO */<br> }<br> break;<br>#elif defined (CONFIG_RALINK_MT7628)<br></div></div><div class="gmail_extra"><br><div class="gmail_quote">2015-10-05 18:11 GMT+08:00 John Crispin <span dir="ltr"><<a href="mailto:blogic@openwrt.org" target="_blank">blogic@openwrt.org</a>></span>:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi,<br>
<br>
comments inline,<br>
<br>
On 22/09/2015 15:26, Michael Lee wrote:<br>
> From: michael lee <<a href="mailto:igvtee@gmail.com">igvtee@gmail.com</a>><br>
><br>
> spi clock is the same as system clock measured by logic analyzer.<br>
><br>
> Signed-off-by: Michael Lee <<a href="mailto:igvtee@gmail.com">igvtee@gmail.com</a>><br>
> ---<br>
> .../0012-MIPS-ralink-add-MT7621-support.patch | 29 +++++++++++++++++-----<br>
> 1 file changed, 23 insertions(+), 6 deletions(-)<br>
><br>
> diff --git a/target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch b/target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch<br>
> index 23d3268..bb4a8e1 100644<br>
> --- a/target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch<br>
> +++ b/target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch<br>
> @@ -520,7 +520,7 @@ Signed-off-by: John Crispin <<a href="mailto:blogic@openwrt.org">blogic@openwrt.org</a>><br>
> +}<br>
> --- /dev/null<br>
> +++ b/arch/mips/ralink/mt7621.c<br>
> -@@ -0,0 +1,209 @@<br>
> +@@ -0,0 +1,226 @@<br>
> +/*<br>
> + * This program is free software; you can redistribute it and/or modify it<br>
> + * under the terms of the GNU General Public License version 2 as published<br>
> @@ -553,6 +553,8 @@ Signed-off-by: John Crispin <<a href="mailto:blogic@openwrt.org">blogic@openwrt.org</a>><br>
> +#define SYSC_REG_CUR_CLK_STS 0x44<br>
> +#define CPU_CLK_SEL (BIT(30) | BIT(31))<br>
> +<br>
> ++#define MEMC_REG_BASE 0x5000<br>
> ++<br>
> +#define MT7621_GPIO_MODE_UART1 1<br>
> +#define MT7621_GPIO_MODE_I2C 2<br>
> +#define MT7621_GPIO_MODE_UART3_MASK 0x3<br>
> @@ -645,7 +647,7 @@ Signed-off-by: John Crispin <<a href="mailto:blogic@openwrt.org">blogic@openwrt.org</a>><br>
> + int fbdiv = 0;<br>
> + u32 clk_sts, syscfg;<br>
> + u8 clk_sel = 0, xtal_mode;<br>
> -+ u32 cpu_clk;<br>
> ++ u32 cpu_clk, sys_clk;<br>
> +<br>
> + if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)<br>
> + clk_sel = 1;<br>
> @@ -656,24 +658,39 @@ Signed-off-by: John Crispin <<a href="mailto:blogic@openwrt.org">blogic@openwrt.org</a>><br>
> + cpu_fdiv = ((clk_sts >> 8) & 0x1F);<br>
> + cpu_ffrac = (clk_sts & 0x1F);<br>
> + cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;<br>
> ++ if (((clk_sts >> 16) & 0x7) == 3)<br>
> ++ sys_clk = cpu_clk / 3;<br>
> ++ else<br>
> ++ sys_clk = cpu_clk / 4;<br>
> + break;<br>
> +<br>
> + case 1:<br>
> -+ fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;<br>
> ++ fbdiv = ((rt_sysc_r32(MEMC_REG_BASE + 0x648) >> 4) & 0x7F) + 1;<br>
> + syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);<br>
> + xtal_mode = (syscfg >> 6) & 0x7;<br>
> + if(xtal_mode >= 6) { //25Mhz Xtal<br>
> + cpu_clk = 25 * fbdiv * 1000 * 1000;<br>
> + } else if(xtal_mode >=3) { //40Mhz Xtal<br>
> -+ cpu_clk = 40 * fbdiv * 1000 * 1000;<br>
> ++ cpu_clk = 20 * fbdiv * 1000 * 1000;<br>
<br>
this looks wrong. can you confirm that this is intentional and not a typo ?<br>
<br>
<br>
<br>
> + } else { // 20Mhz Xtal<br>
> + cpu_clk = 20 * fbdiv * 1000 * 1000;<br>
> + }<br>
> ++ if (syscfg & BIT(5))<br>
> ++ sys_clk = cpu_clk / 4;<br>
> ++ else<br>
> ++ sys_clk = cpu_clk / 3;<br>
> + break;<br>
> + }<br>
> -+ cpu_clk = 880000000;<br>
> ++<br>
> ++#define RFMT(label) label ":%u.%03uMHz "<br>
> ++#define RINT(x) ((x) / 1000000)<br>
> ++#define RFRAC(x) (((x) / 1000) % 1000)<br>
> ++ pr_debug(RFMT("CPU") RFMT("SYS"),<br>
> ++ RINT(cpu_clk), RFRAC(cpu_clk),<br>
> ++ RINT(sys_clk), RFRAC(sys_clk));<br>
> ++<br>
> + ralink_clk_add("cpu", cpu_clk);<br>
> -+ ralink_clk_add("1e000b00.spi", 50000000);<br>
> ++ ralink_clk_add("1e000b00.spi", sys_clk);<br>
> + ralink_clk_add("1e000c00.uartlite", 50000000);<br>
> + ralink_clk_add("1e000d00.uart", 50000000);<br>
> +}<br>
><br>
</blockquote></div><br></div>