<div dir="ltr">This patch is to add support for qca955x_eth_rx_delay to work with the qca955x SoC.<br><br>Signed-off-by: Chris R Blake <<a href="mailto:chrisrblake93@gmail.com">chrisrblake93@gmail.com</a>><br><br>---<br>diff -rupN a/target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay.patch b/target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay.patch<br>--- a/target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay.patch 1969-12-31 18:00:00.000000000 -0600<br>+++ b/target/linux/ar71xx/patches-4.1/742-MIPS-ath79-add-qca955x-mac-tx-rx-delay.patch 2015-09-17 07:50:06.000000000 -0500<br>@@ -0,0 +1,58 @@<br>+--- a/arch/mips/ath79/dev-eth.c<br>++++ b/arch/mips/ath79/dev-eth.c<br>+@@ -823,6 +825,32 @@<br>+ iounmap(base);<br>+ }<br>+<br>++void __init ath79_setup_qca955x_eth_rx_delay(unsigned int rxd,<br>++      unsigned int rxdv)<br>++{<br>++ void __iomem *base;<br>++ u32 t;<br>++<br>++ rxd &= QCA955X_ETH_CFG_RXD_DELAY_MASK;<br>++ rxdv &= QCA955X_ETH_CFG_RDV_DELAY_MASK;<br>++<br>++ base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);<br>++<br>++ t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);<br>++<br>++ t &= ~(QCA955X_ETH_CFG_RXD_DELAY_MASK << QCA955X_ETH_CFG_RXD_DELAY_SHIFT |<br>++       QCA955X_ETH_CFG_RDV_DELAY_MASK << QCA955X_ETH_CFG_RDV_DELAY_SHIFT);<br>++<br>++ t |= (rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT |<br>++      rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT);<br>++<br>++ __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);<br>++ /* flush write */<br>++ __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);<br>++<br>++ iounmap(base);<br>++}<br>++<br>+ static int ath79_eth_instance __initdata;<br>+ void __init ath79_register_eth(unsigned int id)<br>+ {<br>+--- a/arch/mips/ath79/dev-eth.h<br>++++ b/arch/mips/ath79/dev-eth.h<br>+@@ -49,5 +49,6 @@<br>+ void ath79_setup_ar934x_eth_cfg(u32 mask);<br>+ void ath79_setup_ar934x_eth_rx_delay(unsigned int rxd, unsigned int rxdv);<br>+ void ath79_setup_qca955x_eth_cfg(u32 mask);<br>++void ath79_setup_qca955x_eth_rx_delay(unsigned int rxd, unsigned int rxdv);<br>+<br>+ #endif /* _ATH79_DEV_ETH_H */<br>+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h<br>++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h<br>+@@ -1098,5 +1098,11 @@<br>+<br>+ #define QCA955X_ETH_CFG_RGMII_EN BIT(0)<br>+ #define QCA955X_ETH_CFG_GE0_SGMII BIT(6)<br>++#define QCA955X_ETH_CFG_RXD_DELAY BIT(14)<br>++#define QCA955X_ETH_CFG_RXD_DELAY_MASK 0x3<br>++#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT 14<br>++#define QCA955X_ETH_CFG_RDV_DELAY BIT(16)<br>++#define QCA955X_ETH_CFG_RDV_DELAY_MASK 0x3<br>++#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT 16<br>+<br>+ #endif /* __ASM_MACH_AR71XX_REGS_H */<br></div>