<p dir="ltr">Florian<br>
On Jun 5, 2015 2:18 PM, "Dave Taht" <<a href="mailto:dave.taht@bufferbloat.net">dave.taht@bufferbloat.net</a>> wrote:<br>
><br>
> TX delay setting? What else can it do?</p>
<p dir="ltr">This is a delay between the transmit data lines and the transmit clock on a RGMII interface. Based on PCB designs, this is something that may have to be configured to align clock and data lines in a way that does not violate timings and causes packet losses between the MAC and the PHY. These delays are not valid when a RGMII interface operates at 10 or 100Mbits/sec since the clock becomes slow enough the rise and fall times of the data lines are negligable.</p>
<p dir="ltr">><br>
> My dream has been to find a way to set the tx completion interrupt<br>
> to only return with a soft set rate. So if I had a gigE connection<br>
> but my uplink was only 10Mbits, it would return the interrupt<br>
> after 1.3ms had expired.</p>
<p dir="ltr">What you are referring to here is interrupt coalescing, which is different and implemented at the Ethernet MAC and DMA engine levels and not all controllers support that.</p>
<p dir="ltr">><br>
> this would let me get away entirely from using software rate limiting<br>
> with htb, just program a register once with the uplink rate, and<br>
> let bql and fq_codel handle the rest.<br>
><br>
> On Wed, Jun 03, 2015 at 05:20:22PM +0200, Christian Lamparter wrote:<br>
> > The mynet range extender hardware is suffering from ethernet<br>
> > link loss when booting with a recent openwrt image. This only<br>
> > happens on 100mbps links, with 1Gbps speed the link was fine.<br>
> ><br>
> > The cause of the problem is that the AR8035 PHY (aka F1E)<br>
> > requires turning on and off the special TX delay setting<br>
> > depending on the speed of the link.<br>
> ><br>
> > The 10mbps mode only needed the proper pll value, which was<br>
> > extracted from the vendor code.<br>
> ><br>
> > Reported-by: Pascal Paradis<br>
> > Signed-off-by: Christian Lamparter <<a href="mailto:chunkeey@googlemail.com">chunkeey@googlemail.com</a>><br>
> > ---<br>
> > .../ar71xx/files/arch/mips/ath79/mach-mynet-rext.c | 20 ++++++++<br>
> > ...t-phy-at803x-allow-to-configure-via-pdata.patch | 53 ++++++++++++++++++++--<br>
> > 2 files changed, 69 insertions(+), 4 deletions(-)<br>
> ><br>
> > diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mynet-rext.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mynet-rext.c<br>
> > index 02d168e..3d48ca8 100644<br>
> > --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-mynet-rext.c<br>
> > +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mynet-rext.c<br>
> > @@ -14,6 +14,7 @@<br>
> > #include <linux/platform_device.h><br>
> > #include <linux/ath9k_platform.h><br>
> > #include <linux/ar8216_platform.h><br>
> > +#include <linux/platform_data/phy-at803x.h><br>
> ><br>
> > #include <asm/mach-ath79/ar71xx_regs.h><br>
> ><br>
> > @@ -124,6 +125,21 @@ static struct gpio_keys_button mynet_rext_gpio_keys[] __initdata = {<br>
> > },<br>
> > };<br>
> ><br>
> > +static struct at803x_platform_data mynet_rext_at803x_data = {<br>
> > + .disable_smarteee = 0,<br>
> > + .enable_rgmii_rx_delay = 1,<br>
> > + .enable_rgmii_tx_delay = 0,<br>
> > + .fixup_rgmii_tx_delay = 1,<br>
> > +};<br>
> > +<br>
> > +static struct mdio_board_info mynet_rext_mdio0_info[] = {<br>
> > + {<br>
> > + .bus_id = "ag71xx-mdio.0",<br>
> > + .phy_addr = 4,<br>
> > + .platform_data = &mynet_rext_at803x_data,<br>
> > + },<br>
> > +};<br>
> > +<br>
> > static void mynet_rext_get_mac(const char *name, char *mac)<br>
> > {<br>
> > u8 *nvram = (u8 *) KSEG1ADDR(MYNET_REXT_NVRAM_ADDR);<br>
> > @@ -169,12 +185,16 @@ static void __init mynet_rext_setup(void)<br>
> ><br>
> > ath79_register_mdio(0, 0x0);<br>
> ><br>
> > + mdiobus_register_board_info(mynet_rext_mdio0_info,<br>
> > + ARRAY_SIZE(mynet_rext_mdio0_info));<br>
> > +<br>
> > /* LAN */<br>
> > mynet_rext_get_mac("et0macaddr=", ath79_eth0_data.mac_addr);<br>
> ><br>
> > /* GMAC0 is connected to an external PHY on Port 4 */<br>
> > ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;<br>
> > ath79_eth0_data.phy_mask = BIT(4);<br>
> > + ath79_eth0_pll_data.pll_10 = 0x00001313; /* athrs_mac.c */<br>
> > ath79_eth0_pll_data.pll_1000 = 0x0e000000; /* athrs_mac.c */<br>
> > ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;<br>
> > ath79_register_eth(0);<br>
> > diff --git a/target/linux/ar71xx/patches-3.18/425-net-phy-at803x-allow-to-configure-via-pdata.patch b/target/linux/ar71xx/patches-3.18/425-net-phy-at803x-allow-to-configure-via-pdata.patch<br>
> > index babc695..d046ede 100644<br>
> > --- a/target/linux/ar71xx/patches-3.18/425-net-phy-at803x-allow-to-configure-via-pdata.patch<br>
> > +++ b/target/linux/ar71xx/patches-3.18/425-net-phy-at803x-allow-to-configure-via-pdata.patch<br>
> > @@ -32,6 +32,14 @@<br>
> > #define AT803X_DEBUG_SYSTEM_MODE_CTRL 0x05<br>
> > #define AT803X_DEBUG_RGMII_TX_CLK_DLY BIT(8)<br>
> ><br>
> > +@@ -50,6 +60,7 @@ MODULE_LICENSE("GPL");<br>
> > + struct at803x_priv {<br>
> > + bool phy_reset:1;<br>
> > + struct gpio_desc *gpiod_reset;<br>
> > ++ int prev_speed;<br>
> > + };<br>
> > +<br>
> > + struct at803x_context {<br>
> > @@ -61,6 +71,43 @@ struct at803x_context {<br>
> > u16 led_control;<br>
> > };<br>
> > @@ -120,16 +128,53 @@<br>
> > return 0;<br>
> > }<br>
> ><br>
> > +@@ -258,6 +334,8 @@ static int at803x_config_intr(struct phy<br>
> > + static void at803x_link_change_notify(struct phy_device *phydev)<br>
> > + {<br>
> > + struct at803x_priv *priv = phydev->priv;<br>
> > ++ struct at803x_platform_data *pdata;<br>
> > ++ pdata = dev_get_platdata(&phydev->dev);<br>
> > +<br>
> > + /*<br>
> > + * Conduct a hardware reset for AT8030 every time a link loss is<br>
> > +@@ -287,6 +365,26 @@ static void at803x_link_change_notify(st<br>
> > + } else {<br>
> > + priv->phy_reset = false;<br>
> > + }<br>
> > ++ }<br>
> > ++ if (pdata->fixup_rgmii_tx_delay &&<br>
> > ++ phydev->speed != priv->prev_speed) {<br>
> > ++ switch (phydev->speed) {<br>
> > ++ case SPEED_10:<br>
> > ++ case SPEED_100:<br>
> > ++ at803x_dbg_reg_set(phydev,<br>
> > ++ AT803X_DEBUG_SYSTEM_MODE_CTRL,<br>
> > ++ AT803X_DEBUG_RGMII_TX_CLK_DLY);<br>
> > ++ break;<br>
> > ++ case SPEED_1000:<br>
> > ++ at803x_dbg_reg_clr(phydev,<br>
> > ++ AT803X_DEBUG_SYSTEM_MODE_CTRL,<br>
> > ++ AT803X_DEBUG_RGMII_TX_CLK_DLY);<br>
> > ++ break;<br>
> > ++ default:<br>
> > ++ break;<br>
> > ++ }<br>
> > ++<br>
> > ++ priv->prev_speed = phydev->speed;<br>
> > + }<br>
> > + }<br>
> > +<br>
> > --- /dev/null<br>
> > +++ b/include/linux/platform_data/phy-at803x.h<br>
> > -@@ -0,0 +1,10 @@<br>
> > +@@ -0,0 +1,11 @@<br>
> > +#ifndef _PHY_AT803X_PDATA_H<br>
> > +#define _PHY_AT803X_PDATA_H<br>
> > +<br>
> > +struct at803x_platform_data {<br>
> > -+ int disable_smarteee:1;<br>
> > -+ int enable_rgmii_tx_delay:1;<br>
> > -+ int enable_rgmii_rx_delay:1;<br>
> > ++ int disable_smarteee:1;<br>
> > ++ int enable_rgmii_tx_delay:1;<br>
> > ++ int enable_rgmii_rx_delay:1;<br>
> > ++ int fixup_rgmii_tx_delay:1;<br>
> > +};<br>
> > +<br>
> > +#endif /* _PHY_AT803X_PDATA_H */<br>
> > --<br>
> > 2.1.4<br>
> > _______________________________________________<br>
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</p>