[OpenWrt-Devel] ramips/mt7621 after 5.4 switch
Sergio Paracuellos
sergio.paracuellos at gmail.com
Wed Apr 8 00:28:23 EDT 2020
Hi Andre,
On Tue, Apr 7, 2020 at 9:28 PM Andre Valentin <avalentin at marcant.net> wrote:
>
> Am 07.04.20 um 20:05 schrieb Sergio Paracuellos:
> > Hi,
> >
> > On Tue, Apr 7, 2020 at 12:16 PM Chuanhong Guo <gch981213 at gmail.com> wrote:
> >>
> >> [CC Sergio who worked on upstream PCIE driver]
> >>
> >> On Tue, Apr 7, 2020 at 4:45 PM Andre Valentin <avalentin at marcant.net> wrote:
> >>>
> >>> Hi!
> >>>
> >>> Currently I'm having some serious problems with the new 5.4 port.
> >>> 1) PCIe
> >>> I'm developing on the ZyXEL LTE3301-PLUS. It has PCIe and a mt7615e connected to second bus on the first phy.
> >>> If booting the device, kernel hangs with a RST message, telling the device is not detected. It seems the PCIe bus 1
> >>> cannot be reseted because nothing is connected to bus 0.
> >>> An upport of the old PCI driver reenables the function. I can provide more logs on this if needed.
> >
> > Logs and dmesg traces are always welcome and would be helpful. Both
> > working and not working traces.
>
> Of course, here we go with the old PCIe driver taken from 4.14 openwrt kernel:
> [ 0.485729] pinctrl core: add 0 pinctrl maps
> [ 0.485865] pull PCIe RST: RALINK_RSTCTRL = 4000000
> [ 0.796015] release PCIe RST: RALINK_RSTCTRL = 7000000
> [ 0.806088] ***** Xtal 40MHz *****
> [ 0.812829] release PCIe RST: RALINK_RSTCTRL = 7000000
> [ 0.823025] Port 0 N_FTS = 1b102800
> [ 0.829933] Port 1 N_FTS = 1b105000
> [ 0.836849] Port 2 N_FTS = 1b102800
> [ 1.995991] PCIE0 no card, disable it(RST&CLK)
> [ 2.004682] PCIE2 no card, disable it(RST&CLK)
> [ 2.013495] -> 20107f2
> [ 2.018328] PCIE1 enabled
> [ 2.023532] PCI host bridge /pcie at 1e140000 ranges:
> [ 2.033045] MEM 0x0000000060000000..0x000000006fffffff
> [ 2.043401] IO 0x000000001e160000..0x000000001e16ffff
> [ 2.053762] PCI coherence region base: 0xbfbf8000, mask/settings: 0x60000000
> [ 2.091056] PCI host bridge to bus 0000:00
> [ 2.099131] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff]
> [ 2.112734] pci_bus 0000:00: root bus resource [io 0xffffffff]
> [ 2.124486] pci_bus 0000:00: root bus resource [??? 0x00000000 flags 0x0]
> [ 2.137962] pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
> [ 2.153766] pci 0000:00:00.0: [0e8d:0801] type 01 class 0x060400
> [ 2.165651] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x7fffffff]
> [ 2.178057] pci 0000:00:00.0: reg 0x14: [mem 0x60100000-0x6010ffff]
> [ 2.190585] pci 0000:00:00.0: supports D1
> [ 2.198439] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
> [ 2.211463] random: fast init done
> [ 2.211838] pci 0000:01:00.0: [14c3:7615] type 00 class 0x000280
> [ 2.230071] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit]
> [ 2.243675] pci 0000:01:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s x1 link at 0000:00:00.0 (capable of 4.000 Gb/s with 5 GT/s x1 link)
> [ 2.272296] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
> [ 2.285339] pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to 01
> [ 2.298493] pci 0000:00:00.0: BAR 0: no space for [mem size 0x80000000]
> [ 2.311581] pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x80000000]
> [ 2.325410] pci 0000:00:00.0: BAR 8: assigned [mem 0x60000000-0x600fffff]
> [ 2.338888] pci 0000:00:00.0: BAR 1: assigned [mem 0x60100000-0x6010ffff]
> [ 2.352376] pci 0000:01:00.0: BAR 0: assigned [mem 0x60000000-0x600fffff 64bit]
> [ 2.366887] pci 0000:00:00.0: PCI bridge to [bus 01]
> [ 2.376728] pci 0000:00:00.0: bridge window [mem 0x60000000-0x600fffff]
>
>
> And this is on 5.4 with the new driver with pcie0 status=disabled:
> [ 30.464407] mt7621-pci 1e140000.pcie: GPIO lookup for consumer reset
> [ 30.464415] mt7621-pci 1e140000.pcie: using device tree for GPIO lookup
> [ 30.464474] mt7621-pci 1e140000.pcie: using lookup tables for GPIO lookup
> [ 30.464484] mt7621-pci 1e140000.pcie: No GPIO consumer reset found
> [ 30.664239] mt7621-pci 1e140000.pcie: pcie1 no card, disable it (RST & CLK)
> [ 30.678128] mt7621-pci 1e140000.pcie: Nothing is connected in virtual bridges. Exiting...
> booting goes on.
>
> And with pcie status=enabled:
> [ 32.415863] rt2880-pinmux pinctrl: pcie is already enabled
> [ 32.426821] mt7621-pci 1e140000.pcie: Error applying setting, reverse things back
> [ 32.441900] mt7621-pci-phy 1e149000.pcie-phy: PHY for 0xbe149000 (dual port = 1)
> [ 32.456880] mt7621-pci-phy 1e14a000.pcie-phy: PHY for 0xbe14a000 (dual port = 0)
> [ 32.571556] mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
> [ 32.582680] mt7621-pci-phy 1e14a000.pcie-phy: Xtal is 40MHz
> [ 32.693592] mt7621-pci 1e140000.pcie: pcie0 no card, disable it (RST & CLK)
> hangs.
I think the problem here is that upstream driver use two phy's nodes
with pcie-phy0 being a dual ported one.
Because there is nothing connected in pcie0 the phy is just stopped
assuming nothing will be connected also in pcie1.
Just to see if that is the problem, can you please patch the
'mt7621_pcie_init_ports' function and comment the following piece of
code:
if (slot != 1)
phy_power_off(port->phy);
Let's see what happens.
>
>
> DTS Config:
> mt7621.dtsi
> pcie: pcie at 1e140000 {
> compatible = "mediatek,mt7621-pci";
> reg = <0x1e140000 0x100 /* host-pci bridge registers */
> 0x1e142000 0x100 /* pcie port 0 RC control registers */
> 0x1e143000 0x100 /* pcie port 1 RC control registers */
> 0x1e144000 0x100>; /* pcie port 2 RC control registers */
> #address-cells = <3>;
> #size-cells = <2>;
>
> pinctrl-names = "default";
> pinctrl-0 = <&pcie_pins>;
>
> device_type = "pci";
>
> bus-range = <0 255>;
> ranges = <
> 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
> 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
> >;
>
> #interrupt-cells = <1>;
> interrupt-map-mask = <0xF0000 0 0 1>;
> interrupt-map = <0x10000 0 0 1 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
> <0x20000 0 0 1 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
> <0x30000 0 0 1 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
>
> status = "disabled";
>
> resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
> reset-names = "pcie0", "pcie1", "pcie2";
> clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
> clock-names = "pcie0", "pcie1", "pcie2";
> phys = <&pcie0_phy 1>, <&pcie2_phy 0>;
> phy-names = "pcie-phy0", "pcie-phy2";
>
> reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
>
> pcie0: pcie at 0,0 {
> reg = <0x0000 0 0 0 0>;
> #address-cells = <3>;
> #size-cells = <2>;
> ranges;
> bus-range = <0x00 0xff>;
> };
>
> pcie1: pcie at 1,0 {
> reg = <0x0800 0 0 0 0>;
> #address-cells = <3>;
> #size-cells = <2>;
> ranges;
> bus-range = <0x00 0xff>;
> };
>
> pcie2: pcie at 2,0 {
> reg = <0x1000 0 0 0 0>;
> #address-cells = <3>;
> #size-cells = <2>;
> ranges;
> bus-range = <0x00 0xff>;
> };
> };
>
> pcie0_phy: pcie-phy at 1e149000 {
> compatible = "mediatek,mt7621-pci-phy";
> reg = <0x1e149000 0x0700>;
> #phy-cells = <1>;
> };
>
> pcie2_phy: pcie-phy at 1e14a000 {
> compatible = "mediatek,mt7621-pci-phy";
> reg = <0x1e14a000 0x0700>;
> #phy-cells = <1>;
> };
>
> device.dts:
> &pcie {
> status = "okay";
> };
>
> &pcie1 {
> status = "okay";
> mt76 at 0,0 {
> compatible = "pci14c3,7615";
> reg = <0x0000 0 0 0 0>;
> mediatek,mtd-eeprom = <&factory 0x8000>;
> mtd-mac-address = <&factory 0xfe6e>;
> mtd-mac-address-increment = <1>;
> };
> };
>
> Thanks for taking a look!
>
> Kind regards,
>
> André
>
Best regards,
Sergio Paracuellos
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