[OpenWrt-Devel] [PATCH] ramips: mt7621: Fix some cosmetic DTC warnings

[Daniel Golle]

On Thu, Jun 07, 2018 at 10:31:23AM -0700, Rosen Penev wrote:
> Node /cpus/cpu at 0 has a unit name, but no reg property
> Node /cpus/cpu at 1 has a unit name, but no reg property
> Node /cpuintc at 0 has a unit name, but no reg property
> Node /cpuclock at 0 has a unit name, but no reg property
> Node /sysclock at 0 has a unit name, but no reg property
> Node /pcie at 1e140000/pcie0 missing ranges for PCI bridge (or not a bridge)
> Node /pcie at 1e140000/pcie0 missing bus-range for PCI bridge
> Node /pcie at 1e140000/pcie1 missing ranges for PCI bridge (or not a bridge)
> Node /pcie at 1e140000/pcie1 missing bus-range for PCI bridge
> Node /pcie at 1e140000/pcie2 missing ranges for PCI bridge (or not a bridge)
> Node /pcie at 1e140000/pcie2 missing bus-range for PCI bridge

Same here on MT7688AN, we need a sepearte fix for that as well...

> 
> Signed-off-by: Rosen Penev <rosenp at gmail.com>
> ---
>  target/linux/ramips/dts/mt7621.dtsi | 25 ++++++++++++++++---------
>  1 file changed, 16 insertions(+), 9 deletions(-)
> 
> diff --git a/target/linux/ramips/dts/mt7621.dtsi b/target/linux/ramips/dts/mt7621.dtsi
> index daca857f60..59cd4fb171 100644
> --- a/target/linux/ramips/dts/mt7621.dtsi
> +++ b/target/linux/ramips/dts/mt7621.dtsi
> @@ -6,16 +6,23 @@
>  	compatible = "mediatek,mt7621-soc";
>  
>  	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
>  		cpu at 0 {
> +			device_type = "cpu";
>  			compatible = "mips,mips1004Kc";
> +			reg = <0x0>;
>  		};
>  
>  		cpu at 1 {
> +			device_type = "cpu";
>  			compatible = "mips,mips1004Kc";
> +			reg = <0x1>;
>  		};
>  	};
>  
> -	cpuintc: cpuintc at 0 {
> +	cpuintc: cpuintc {
>  		#address-cells = <0>;
>  		#interrupt-cells = <1>;
>  		interrupt-controller;
> @@ -26,7 +33,7 @@
>  		serial0 = &uartlite;
>  	};
>  
> -	cpuclock: cpuclock at 0 {
> +	cpuclock: cpuclock {
>  		#clock-cells = <0>;
>  		compatible = "fixed-clock";
>  
> @@ -34,7 +41,7 @@
>  		clock-frequency = <880000000>;
>  	};
>  
> -	sysclock: sysclock at 0 {
> +	sysclock: sysclock {
>  		#clock-cells = <0>;
>  		compatible = "fixed-clock";
>  
> @@ -454,28 +461,28 @@
>  
>  		pcie0 {
>  			reg = <0x0000 0 0 0 0>;
> -
>  			#address-cells = <3>;
>  			#size-cells = <2>;
> -
> +			ranges;
> +			bus-range = <0 255>;
>  			device_type = "pci";
>  		};
>  
>  		pcie1 {
>  			reg = <0x0800 0 0 0 0>;
> -
>  			#address-cells = <3>;
>  			#size-cells = <2>;
> -
> +			ranges;
> +			bus-range = <0 255>;
>  			device_type = "pci";
>  		};
>  
>  		pcie2 {
>  			reg = <0x1000 0 0 0 0>;
> -
>  			#address-cells = <3>;
>  			#size-cells = <2>;
> -
> +			ranges;
> +			bus-range = <0 255>;
>  			device_type = "pci";
>  		};
>  	};
> -- 
> 2.17.1
> 
> 
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