[OpenWrt-Devel] Subject: [PATCH] [target] Addition of NixCore X1 Board

[Andrew Gaylo]

from: Andrew Gaylo <admin at clisystems.com>

This submission is for a the NixCore X1 board.  This board uses the
RT5350 Ralink processor already supported by a number of board in the
OpenWRT repository.  The DTS and profile MK provided is based on
existing boards included in the repo (VoCore).

Signed-off-by: Andrew Gaylo <admin at clisystems.com>
---
diff -uprN openwrt_vanilla/target/linux/ramips/dts/NIXCORE-X1.dts 
openwrt_submit/target/linux/ramips/dts/NIXCORE-X1.dts
--- openwrt_vanilla/target/linux/ramips/dts/NIXCORE-X1.dts	1969-12-31 
17:00:00.000000000 -0700
+++ openwrt_submit/target/linux/ramips/dts/NIXCORE-X1.dts	2015-10-13 
11:04:19.636954204 -0600
@@ -0,0 +1,186 @@
+/dts-v1/;
+
+/include/ "rt5350.dtsi"
+
+/ {
+	compatible = "NixcoreX1", "ralink,rt5350-soc";
+	model = "NixcoreX1";
+
+	palmbus at 10000000 {
+        /* Re-enable the gpio1 ports */
+		gpio1: gpio at 660 {
+			status = "okay";
+		};
+
+		i2c at 900 {
+			status = "okay";
+		};
+		uart at 500 {
+			status = "okay";
+            /* Mix of uart and gpio */
+            reset-names = "gpio uartf";
+		};
+		spi at b00 {
+			status = "okay";
+
+			m25p80 at 0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "s25fl064k";
+				reg = <0>;
+				linux,modalias = "m25p80", "s25fl064k";
+				spi-max-frequency = <10000000>;
+
+				partition at 0 {
+					label = "uboot";
+					reg = <0x0 0x30000>;
+					read-only;
+				};
+
+				partition at 30000 {
+					label = "uboot-env";
+					reg = <0x30000 0x10000>;
+					read-only;
+				};
+
+				factory: partition at 40000 {
+					label = "factory";
+					reg = <0x40000 0x10000>;
+					read-only;
+				};
+
+				partition at 50000 {
+					label = "firmware";
+					reg = <0x50000 0x7b0000>;
+				};
+			};
+
+			spidev at 1 {
+				compatible = "linux,spidev";
+				spi-max-frequency = <10000000>;
+				reg = <1>;
+			};
+		};
+	};
+
+	pinctrl {
+		state_default: pinctrl0 {
+			gpio {
+                /* Associate the tjag, uartf and led grps with gpio */
+				ralink,group = "jtag", "led", "spi_cs1";
+                /* How do we set individual pins? */
+				ralink,function = "gpio";
+			};
+		};
+	};
+
+	ethernet at 10100000 {
+		mtd-mac-address = <&factory 0x4>;
+	};
+
+	esw at 10110000 {
+		ralink,portmap = <0x17>;
+	};
+
+	wmac at 10180000 {
+		ralink,mtd-eeprom = <&factory 0>;
+	};
+
+	ehci at 101c0000 {
+		status = "okay";
+	};
+
+	ohci at 101c1000 {
+		status = "okay";
+	};
+
+    chosen {
+		bootargs = "console=ttyS1,57600";
+	};
+	gpio-export {
+		compatible = "gpio-export";
+		#size-cells = <0>;
+
+		gpio0 {
+			gpio-export,name = "gpio0";
+			gpio-export,direction_may_change = <1>;
+			gpios = <&gpio0 0 0>;
+		};
+
+        /* GPIOs 1-6 are I2C,SPI */
+
+        /* GPIO 7-14 are uart1 */
+
+        /* GPIOs 15 & 16 are uart2 */
+
+		/* JTAG */
+		gpio17 {
+			/* JTAG_TDO */
+			gpio-export,name = "gpio17";
+			gpio-export,direction_may_change = <1>;
+			gpios = <&gpio0 17 0>;
+		};
+		gpio18 {
+			/* JTAG_TDI */
+			gpio-export,name = "gpio18";
+			gpio-export,direction_may_change = <1>;
+			gpios = <&gpio0 18 0>;
+		};
+		gpio19 {
+			/* JTAG_TMS */
+			gpio-export,name = "gpio19";
+			gpio-export,direction_may_change = <1>;
+			gpios = <&gpio0 19 0>;
+		};
+		gpio20 {
+			/* JTAG_TCLK */
+			gpio-export,name = "gpio20";
+			gpio-export,direction_may_change = <1>;
+			gpios = <&gpio0 20 0>;
+		};
+		gpio21 {
+			/* JTAG_TRST_N */
+			gpio-export,name = "gpio21";
+			gpio-export,direction_may_change = <1>;
+			gpios = <&gpio0 21 0>;
+		};
+
+		/* ETH LEDs */
+        /*
+        gpio22 {
+			gpio-export,name = "gpio22";
+			gpio-export,direction_may_change = <1>;
+			gpios = <&gpio1 0 0>;
+		};
+        gpio23 {
+			gpio-export,name = "gpio23";
+			gpio-export,direction_may_change = <1>;
+			gpios = <&gpio1 1 0>;
+		};
+        gpio24 {
+			gpio-export,name = "gpio24";
+			gpio-export,direction_may_change = <1>;
+			gpios = <&gpio1 2 0>;
+		};
+		gpio25 {
+			gpio-export,name = "gpio25";
+			gpio-export,direction_may_change = <1>;
+			gpios = <&gpio1 3 0>;
+		};
+        */
+		gpio26 {
+			/* ETH4_LED */
+			gpio-export,name = "gpio26";
+			gpio-export,direction_may_change = <1>;
+			gpios = <&gpio1 4 0>;
+		};
+
+        gpio27 {
+			/* spi_cs1 */
+			gpio-export,name = "gpio27";
+			gpio-export,direction_may_change = <1>;
+			gpios = <&gpio1 5 0>;
+		};
+	};
+
+};
diff -uprN 
openwrt_vanilla/target/linux/ramips/rt305x/profiles/nixcore.mk 
openwrt_submit/target/linux/ramips/rt305x/profiles/nixcore.mk
--- 
openwrt_vanilla/target/linux/ramips/rt305x/profiles/nixcore.mk	1969-12-31 
17:00:00.000000000 -0700
+++ 
openwrt_submit/target/linux/ramips/rt305x/profiles/nixcore.mk	2015-10-13 
11:04:38.500954359 -0600
@@ -0,0 +1,20 @@
+#
+# Copyright (C) 2014 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License 
v2.
+# See /LICENSE for more information.
+#
+
+define Profile/NIXCORE-X1
+	NAME:=NixcoreX1
+	PACKAGES:=\
+		kmod-usb-core kmod-usb-ohci kmod-usb2 \
+		kmod-i2c-core kmod-i2c-ralink \
+		kmod-spi-dev
+endef
+
+define Profile/NIXCORE-X1/Description
+	Package set for Nixcore X1 board
+endef
+
+$(eval $(call Profile,NIXCORE-X1))
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