[OpenWrt-Devel] Need help understanding Ralink's dts config file and how it works

[Sławomir Demeszko]

On  23.11.2014 17:05, Md Mahbubur Rasheed wrote:

Hi, I am also currently working on board with this chip, and answers to your question will 
be helpful for me too. I can share my knowledge, but don't treat this as an axiom, I am 
begginer in this subject too and I could be wrong.

> 1. Why a single SoC has so many  built in ethernet controllers/
 > drivers (MT7530, RT2880, MT7620)? If a doesn't have any external
 > ethernet controller, then which one should we use?
I think that MT7530 is a name of internal or external switch and driver for it. RT2880 is 
an older SoC created by Ralink which was taken few years ago by Mediatek and few things 
are compatible with MT7620A, so drivers stay the same. And MT7620 is actual name of SoC. 
In .dts files we define among others things which device are comatible to already 
supported devices, that way if there isn't more specific driver for certain device, less 
specific or general can be used.

> But configurations, such as-  ethernet at 10100000 , pinctrl etc remain
 > as foggy as it was 12 hours ago.
As I know "ethernet at 10100000" is only a name. Real address of register of device is passed 
by "reg" field. But also included in name for convience.

> 2. How (and where) is the WAN  port (i.e. phy4) mapped to gigabit bus
 > rgmii? Is it possible to map WAN port as a gigabit port? Or it always
 > remains 100Mbps port?
Electrical WAN or LAN (opposed to virtual defined in /etc/config/network) depends on 
connection on board and usually all mechanical ports are connected to 100Mbps ports of 
internal switch (by internal "EPHY" component). MT7620A has 5 that ports and 2x 1Gbps, but 
these two are RGMII ports and need additional chip (a PHY) to be possible for connection 
of external devices.

> 3. In the following code, when  should we use gmac and when ephy?
 > gsw at 10110000 { ralink,port4 = "gmac"; };
I guess that "ephy" means that specified SoC port is connected to some external "EPHY" 
chip by RGMII or other interface and "gmac" not.

> 4. what does the following code  do? pinctrl { state_default: pinctrl0
 > { gpio { ralink,group = "i2c", "uartf"; ralink,function = "gpio"; };
 > }; };
I am also don't know. Some info can be found at kernel 
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt and parent directory.

> Finally, the MT7620A  programming guide describes the registers, but
 > it doesn't explain the configurations or provides examples. I tried
 > to use dts files for other routers to understand, but it was not much
 > fruitful either. Is there any resource explaining the structure and
 > programming model?
I think that almost everything about SoC itself is defined already in mt7620a.dtsi and 
implemented in drivers, so we not need to worry about all these internal stuff. But SoC 
can be connected on board with different configurations, using different protocols, 
different external chips and that depends on specific board. We do not always have access 
to documentation how board is contructed and I think other developers use method of trial 
and error, or by tracking paths on board, or by analyzing original firmware. Quite 
detailed documentation is in kernel sources at Documentation/devicetree. Here is a link: 
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree
_______________________________________________
openwrt-devel mailing list
openwrt-devel at lists.openwrt.org
https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel