[PATCH 5/5] platform: generic: eswin: Add feature_config_init op for L1_HWPF override

[Leo Yu-Chi Liang]

Introduce a feature_config_init operation for the eic770x platform
that delegates to generic_feature_config_init() for the vendor
defaults and overrides the HW prefetcher bits on top via
sbi_hart_feature_config_set().

Remove the direct, unconditional writes to the FEAT0/FEAT1/L1_HWPF/
L2_HWPF CSRs from eswin_eic7700_final_init(), now handled through the
feature_config_init operation instead.

Drop the platform-local EIC770X_CSR_* macros, now redundant with the
shared definitions in sifive_feature_config.h, and switch
eic770x_hart_stop() to use SIFIVE_CSR_FEATURE_CONFIG in place of
EIC770X_CSR_FEAT0.

Signed-off-by: Leo Yu-Chi Liang <leo.liang at sifive.com>
Assisted-by: LLM
---
 platform/generic/eswin/eic770x.c         | 36 +++++++++++++++---------
 platform/generic/include/eswin/eic770x.h |  7 -----
 2 files changed, 22 insertions(+), 21 deletions(-)

diff --git a/platform/generic/eswin/eic770x.c b/platform/generic/eswin/eic770x.c
index c71198a8..ceefb50f 100644
--- a/platform/generic/eswin/eic770x.c
+++ b/platform/generic/eswin/eic770x.c
@@ -6,15 +6,19 @@
  */
 
 #include <platform_override.h>
+#include <sbi/riscv_asm.h>
 #include <sbi/riscv_io.h>
 #include <sbi/sbi_console.h>
 #include <sbi/sbi_system.h>
 #include <sbi/sbi_math.h>
 #include <sbi/sbi_hart.h>
+#include <sbi/sbi_hart_feature_config.h>
 #include <sbi/sbi_hsm.h>
 #include <sbi/sbi_ipi.h>
 #include <sbi/sbi_hart_pmp.h>
 #include <sbi/sbi_hart_protection.h>
+#include <sbi/sbi_platform.h>
+#include <sbi_utils/feature/sifive_feature_config.h>
 #include <sbi_utils/hsm/fdt_hsm_sifive_inst.h>
 #include <eswin/eic770x.h>
 #include <eswin/hfp.h>
@@ -51,13 +55,13 @@ static int eic770x_hart_stop()
 	 * When some or all warm boot harts haven't gone under at least 1
 	 * cycle of hsm start/stop, (happens if reset is issued in pre-
 	 * boot environment u-boot/UEFI where all warm boot harts are
-	 * pending start), the FEAT0 CSR still holds the SoC reset values,
-	 * and disableDCacheClockGate is set. A CEASE instruction executed
-	 * when disableDCacheClockGate=1 will not properly reflect its
-	 * ceased status in mcput_cease_from_tile_x. Thus, clear it before
-	 * CEASE.
+	 * pending start), the FEATURE_CONFIG CSR still holds the SoC reset
+	 * values, and disableDCacheClockGate is set. A CEASE instruction
+	 * executed when disableDCacheClockGate=1 will not properly reflect
+	 * its ceased status in mcput_cease_from_tile_x. Thus, clear it
+	 * before CEASE.
 	 */
-	csr_clear(EIC770X_CSR_FEAT0, 0x1);
+	csr_clear(SIFIVE_CSR_FEATURE_CONFIG, 0x1);
 
 	sifive_cease();
 }
@@ -368,18 +372,21 @@ static int eswin_eic7700_final_init(bool cold_boot)
 
 	sbi_hart_pmp_set(PMP_RESERVED_B, PMP_L, 0,
 			 log2roundup(EIC770X_MEMPORT_LIMIT));
-	/**
-	 * These must come after the setup of PMP, as we are about to
-	 * enable speculation and HW prefetcher bits
-	 */
-	csr_write(EIC770X_CSR_FEAT0, CONFIG_ESWIN_EIC770X_FEAT0_CFG);
-	csr_write(EIC770X_CSR_FEAT1, CONFIG_ESWIN_EIC770X_FEAT1_CFG);
-	csr_write(EIC770X_CSR_L1_HWPF, CONFIG_ESWIN_EIC770X_L1_HWPF_CFG);
-	csr_write(EIC770X_CSR_L2_HWPF, CONFIG_ESWIN_EIC770X_L2_HWPF_CFG);
 
 	return 0;
 }
 
+static int eic770x_feature_config_init(bool cold_boot)
+{
+	int rc = generic_feature_config_init(cold_boot);
+
+	if (rc)
+		return rc;
+
+	return sbi_hart_feature_config_set(current_hartindex(), SIFIVE_CSR_HWPF_CONFIG,
+					   CONFIG_ESWIN_EIC770X_L1_HWPF_CFG, false);
+}
+
 static int eswin_eic7700_pmp_configure(struct sbi_scratch *scratch,
 				       struct sbi_domain *dom)
 {
@@ -486,6 +493,7 @@ static int eswin_eic7700_platform_init(const void *fdt, int nodeoff,
 	const struct eic770x_board_override *board_override = match->data;
 
 	generic_platform_ops.early_init = eswin_eic7700_early_init;
+	generic_platform_ops.feature_config_init = eic770x_feature_config_init;
 	generic_platform_ops.final_init = eswin_eic7700_final_init;
 	generic_platform_ops.single_fw_region = eswin_eic7700_single_fw_region;
 
diff --git a/platform/generic/include/eswin/eic770x.h b/platform/generic/include/eswin/eic770x.h
index 9c80b589..58d317d0 100644
--- a/platform/generic/include/eswin/eic770x.h
+++ b/platform/generic/include/eswin/eic770x.h
@@ -16,13 +16,6 @@ struct eic770x_board_override {
 
 void eic770x_cease_other_harts(void);
 
-/* CSRs */
-#define EIC770X_CSR_BRPREDICT	0x7c0
-#define EIC770X_CSR_FEAT0	0x7c1
-#define EIC770X_CSR_FEAT1	0x7c2
-#define EIC770X_CSR_L1_HWPF	0x7c3
-#define EIC770X_CSR_L2_HWPF	0x7c4
-
 /* Hart ID to core/die conversion */
 #define CPU_CORE_BITS		2
 #define CPU_CORE_MASK		((1 << CPU_CORE_BITS) - 1)
-- 
2.43.7