[PATCH] lib: utils/cache: andes_llcache: match andestech,ax45mp-cache

[Randolph]

The Linux binding for the AX45MP L2 cache controller,
andestech,ax45mp-cache.yaml, uses the "andestech,ax45mp-cache"
compatible, and the RZ/Five and QiLai device trees follow it. No
binding defines "andestech,llcache", so this driver does not probe the
L2 cache on these boards. OpenSBI then uses a generic cache device,
which cannot flush or enable the cache.

The AX45MP L2 cache controller has the registers this driver uses: the
memory map bit in the config register, the init status bit in the
control register, and the per-core CCTL command and status registers.
Add the compatible to the match table.

Assisted-by: Claude:claude-opus-5-5
Signed-off-by: Randolph Lin <randolph at andestech.com>
---
 lib/utils/cache/fdt_andes_llcache.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/lib/utils/cache/fdt_andes_llcache.c b/lib/utils/cache/fdt_andes_llcache.c
index 7a61b6ab..c32ff2aa 100644
--- a/lib/utils/cache/fdt_andes_llcache.c
+++ b/lib/utils/cache/fdt_andes_llcache.c
@@ -172,6 +172,7 @@ static int andes_llcache_probe(const void *fdt, int nodeoff, const struct fdt_ma
 
 static const struct fdt_match andes_llcache_match[] = {
 	{ .compatible = "andestech,llcache" },
+	{ .compatible = "andestech,ax45mp-cache" },
 	{},
 };
 
-- 
2.34.1