[RFC PATCH v3 0/6] Preserve more architectural state across domain switches

[Theodorus Wensan Februanto]

This RFC series extends OpenSBI domain context switching to preserve
additional architectural state, including hypervisor, virtual supervisor,
supervisor timer, counter configuration, indirect CSR selector,
control transfer recording, and vector state.

Changes since v2:
- Combine the hypervisor and optional H-extension patches.
- Save outgoing VS state before switching H-extension interrupt state,
  then restore incoming VS state afterward.
- Include RV32 vsieh/vsiph and the optional hvien, hvictl,
  hviprio1, and hviprio2 registers.
- Preserve siselect when Sscsrind or Smaia is available.
  Also preserve vsiselect when H is implemented under this condition.
- Remove the supervisor AIA interrupt priority patch pending
  further discussion of per-domain AIA ownership and access control.
- Grow CTR buffers when the active depth exceeds the allocated
  capacity, avoiding silent loss of CTR records.
- Fix the RV32 build warning in the CTR implementation.
- Rebase onto OpenSBI master at 332798211e7232da60158b0545b23c61b5338516.
  The upstream FP state-enable fix is already included in this base.

Testing:
- OpenSBI generic platform builds: PASS on RV64 and RV32.
- QEMU RV64 with H, F, D, V, Smaia, and Ssaia enabled.
- 16 H/VS CSR test cases passed:
  - 7 single-context CSR access and value checks.
  - 9 A -> B -> A domain context-switch checks.
  - Covers hcounteren, hvictl, hvien, hviprio1/2,
    and interactions involving hideleg, hie, hvip,
    vsie, and vsip.
- 2 additional A -> B -> A test cases passed:
  - siselect preservation.
  - vsiselect preservation.
- Total H/VS and selector results: 18 PASS, 0 FAIL.

CTR testing:
- QEMU RV64 with Smctr, Ssctr, Smcsrind, and Sscsrind enabled.
- Verified support for 256 CTR entries through sctrdepth.
- Reproduced loss of CTR entry 16 with the initial buffer
  allocation based on the boot-time depth.
- Added dynamic buffer growth based on the active CTR depth.
- A 37 KiB firmware heap was insufficient for the tested
  256-entry CTR configuration and resulted in SBI_ENOMEM.
- With a 96 KiB firmware heap, CTR entry 16 was successfully
  preserved across an A -> B -> A domain switch.
- QEMU completed the CTR reproduction successfully.

Limitations:
- RV32 runtime behavior has not been tested.
- CTR runtime testing covers selected behavior, not all CTR state.
- Sstc, supervisor count inhibit, and vector preservation
  have not been tested separately.
- CTR heap requirements depend on the number of domains and harts.
- Per-domain AIA ownership and IMSIC state switching are not
  implemented by this series.

AIA scope:
This series preserves selected H/VS interrupt CSRs and indirect CSR
selectors. It does not implement per-domain AIA ownership, IMSIC state
switching, or access restrictions for domains sharing a hart.

Preserving the indirect CSR selectors does not preserve the
indirectly selected register banks.

I would appreciate feedback on whether the remaining Smaia-related
CSR preservation should stay in this series while the per-domain
AIA ownership design remains open.

Link: https://github.com/riscv-software-src/opensbi/issues/433
Link: https://github.com/riscv-software-src/opensbi/issues/434

Theodorus Wensan Februanto (6):
  lib: sbi: Preserve hypervisor and VS state across domain switches
  lib: sbi: Preserve Sstc timer state across domain switches
  lib: sbi: Preserve supervisor count inhibit configuration
  lib: sbi: Preserve S/VS indirect CSR selectors
  lib: sbi: Preserve supervisor CTR records across domain switches
  lib: sbi: Preserve vl and vtype during domain switches

 include/sbi/riscv_encoding.h |   2 +
 include/sbi/sbi_hart.h       |   2 +
 include/sbi/sbi_vector.h     |   2 +
 lib/sbi/sbi_domain_context.c | 291 +++++++++++++++++++++++++++++++++++
 lib/sbi/sbi_hart.c           |  11 ++
 lib/sbi/sbi_vector.c         |  11 ++
 6 files changed, 319 insertions(+)

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2.43.0