[PATCH v4 0/3] Add eager FP and RISC-V vector context switching support

[Anup Patel]

On Wed, May 13, 2026 at 12:44 PM <dave.patel at riscstar.com> wrote:
>
> Hi Anup,
>         Thank you for taking out time and reviewing the patches.
> Following your review comments, I have made following changes. Also I have
> tested the changes.
>
> The changes include:
>         - Dropping CONFIG_SBI_MAX_VLENB and sbi_vector_domain_init()
>         - struct sbi_vector_context vec_ctx is now struct * in
>           'struct hart_context'
>         - changing READ_CSR and WRITE_CSR to vcsr_read and vcsr_write

I think you misunderstood my previous comment. We already
have csr_read() and csr_write() defined in riscv_asm.h so use
these macros instead of introducing  vcsr_read() and vcsr_write().

>
> I have covered all your comments, please can you have a look and let me know.
>

Regards,
Anup