[PATCH v2] lib: sbi: Allow platforms to override local TLB operations

[Samuel Holland]

Hi,

On 2026-06-17 6:29 AM, Xiang W wrote:
> Some T-Head based processors, for example the Sophgo SG2044, have a
> JTLB errata that requires special handling of certain TLB maintenance
> instructions (sfence.vma).
> 
> Introduce a sbi_tlb_local_operations structure so platforms can provide
> custom local TLB flush implementations. Use it to implement the JTLB
> workaround on affected SoCs (currently Sophgo SG2044).
> 
> Signed-off-by: Xiang W <wangxiang at iscas.ac.cn>
> Signed-off-by: Han Gao <gaohan at iscas.ac.cn>
> ---
>  include/sbi/sbi_tlb.h                        | 31 +++++++++++++
>  lib/sbi/sbi_tlb.c                            | 46 +++++++++++++++++---
>  platform/generic/include/thead/c9xx_errata.h |  1 +
>  platform/generic/thead/thead-generic.c       | 31 ++++++++++++-
>  4 files changed, 101 insertions(+), 8 deletions(-)
> 
> [...]
> +static void thead_jtlb_local_sfence_vma(struct sbi_tlb_info *tinfo)
> +{
> +	sbi_pmu_ctr_incr_fw(SBI_PMU_FW_SFENCE_VMA_RCVD);
> +	__asm__ __volatile__("sfence.vma");
> +}
> +
> +static void thead_jtlb_local_sfence_vma_asid(struct sbi_tlb_info *tinfo)
> +{
> +	sbi_pmu_ctr_incr_fw(SBI_PMU_FW_SFENCE_VMA_ASID_RCVD);
> +	/* Flush entire MM context for a given ASID */
> +	__asm__ __volatile__("sfence.vma x0, %0"
> +			     :
> +			     : "r"(tinfo->asid)
> +			     : "memory");
> +}

This looks similar to the bug seen on older SiFive chips, where we must always
flush the full address space. If so, there is already a much simpler workaround
available, using get_tlbr_flush_limit. See platform/generic/sifive/fu540.c.

Regards,
Samuel