[PATCH 0/7] RISC-V AIA: APLIC and IMSIC irqchip framework integration

[Pawandeep Oza]

From: Oza Pawandeep <pawandeep.oza at oss.qualcomm.com>

This series integrates the RISC-V Advanced Interrupt Architecture (AIA)
APLIC and IMSIC M-mode drivers into the OpenSBI sbi_irqchip framework,
replacing the previous standalone experimental driver with a complete
callback-based implementation.

The series adds full support for:

  - APLIC Direct Mode (IDC) interrupt delivery with per-hart IDC
    register management, priority-based routing, and source delegation
    to S-mode child domains.

  - APLIC MSI Mode fallback where IDC structures are absent, routing
    wired interrupts through IMSIC by programming APLIC TARGET registers
    with hart index, guest index, and dynamically allocated EIIDs.

  - IMSIC instance-based irqchip registration with per-hart interrupt
    file management, EIE CSR state tracking, warm-boot state restoration,
    and MSI composition for upstream APLIC affinity reprogramming.

  - A decoupled architecture between APLIC and IMSIC drivers mediated
    by the sbi_irqchip framework. APLIC registers write_msi and
    msi_callback hooks; IMSIC registers the irqchip MSI sink. Neither
    driver directly references the other's data structures.

  - IRQ enable state tracking in the irqchip framework via a new
    irq_state field and IRQ_ENABLED flag, exposed through
    sbi_irqchip_is_irq_enabled() for warm-boot EIE CSR restoration.

  - A fix for two allocation bugs in sbi_irqchip_register_msi() that
    prevented contiguous EIID allocation when reserved handlers were
    already registered.

Driver initialization follows hardware dependency ordering:

  IMSIC cold init → APLIC cold init

The IMSIC irqchip must be registered before APLIC so that APLIC MSI
mode can resolve the parent chip by unique_id via
sbi_irqchip_find_device() during hwirq_setup.

APLIC Direct Mode and MSI Mode are mutually exclusive and selected
at cold init time based on the presence of IDC structures (num_idc)
and the IMSIC geometry (has_msicfg_mmode) parsed from the Device Tree.

Testing was performed on a QEMU RISC-V platform with 128 harts, two
APLIC domains (M-mode at 0x10010000, S-mode at 0x10018000), and two
IMSIC instances (Hart 0-1 at 0x19e0000, Hart 2-3 at 0x19f0000) with
31 wired interrupt sources. End-to-end M-mode interrupt delivery via
APLIC MSI mode was verified using a software interrupt test client
exercising the GENMSI path.

Pawandeep Oza (7):
  lib: utils/irqchip/aplic: implement direct mode irqchip callbacks
  lib: utils/irqchip/imsic: embed sbi_irqchip_device in imsic data
  lib: utils/irqchip/imsic: track IRQ enable state and restore EIE on
    warm init
  lib: utils/irqchip/imsic: migrate to irqchip framework
  lib: utils/irqchip/aplic: add MSI mode support with IMSIC parent
    linking
  lib: sbi_irqchip: fix MSI EIID gap and tail allocation logic in
    register_msi

 lib/sbi/sbi_irqchip.c               |   4 +-
 lib/utils/irqchip/aplic.c           | 400 ++++++++++++++++++++++++++-
 lib/utils/irqchip/aplic.h           |  30 ++
 lib/utils/irqchip/imsic.c           | 350 +++++++++++++++++++++++--
 lib/utils/irqchip/imsic.h           |   5 +-
 include/sbi/sbi_irqchip.h           |  20 ++
 6 files changed, 780 insertions(+), 9 deletions(-)

-- 
2.43.0