[PATCH v2 0/2] Fix eic770x warm reset

[Anup Patel]

On Fri, Jun 5, 2026 at 2:10 PM Bo Gan <ganboing at gmail.com> wrote:
>
> Use the CEASE instruction as documented in the SoC datasheet to fix
> the warm reset issue observed on my EIC7700/Hifive P550. Refer to
> PATCH 2/2 for a more detailed description.
>
> Signed-off-by: Bo Gan <ganboing at gmail.com>
> ---
> Changes in v2:
>  - Clear the disableDCacheClockGate bit in EIC770X_CSR_FEAT0
>    See more detailed comments in function eic770x_hart_stop
>
> ---
> Bo Gan (2):
>   include: utils/hsm: Add __noreturn attribute for sifive_cease
>   platform: generic: eswin: Add eic770x_hsm and fix warm reset issues
>
>  include/sbi_utils/hsm/fdt_hsm_sifive_inst.h |   3 +-
>  platform/generic/eswin/eic770x.c            | 118 ++++++++++++++++++--
>  platform/generic/eswin/hfp.c                |   4 +-
>  platform/generic/include/eswin/eic770x.h    |  20 +++-
>  4 files changed, 128 insertions(+), 17 deletions(-)
>

LGTM.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this series to the riscv/opensbi repo.

Thanks,
Anup