[RFC PATCH 02/12] lib: utils: fdt_helper: parse RISC-V Worlds DT properties

[Yu-Chien Peter Lin]

On Wed, Jul 08, 2026 at 05:42:44PM -0700, Pawandeep Oza wrote:
> On Wed, Jul 8, 2026 at 5:36 PM Pawandeep Oza
> <pawandeep.oza at oss.qualcomm.com> wrote:
> >
> > On Fri, Jun 26, 2026 at 3:16 AM Yu-Chien Peter Lin <peter.lin at sifive.com> wrote:
> > >
> > > Add fdt_parse_worlds_all_harts() to parse RISC-V Worlds device tree
> > > properties from CPU nodes:
> > >   - riscv,pmwid (u32): Physical Machine World ID for this hart
> > >   - riscv,pmwidlist (u64): Bitmap of permitted M-mode World IDs
> > >   - riscv,pmlwidlist (u64): Bitmap of permitted S/U-mode World IDs
> > >
> > > This patch extends the sbi_hart_features struct with new fields to
> > > store the parsed World ID configuration (has_pmwid, pmwid, pmwidlist,
> > > and pmlwidlist).
> > >
> > > Link: https://lore.kernel.org/all/20260619105834.1277302-3-peter.lin@sifive.com/
> > > Signed-off-by: Yu-Chien Peter Lin <peter.lin at sifive.com>
> > > ---
> > >  include/sbi/sbi_hart.h             | 15 ++++++++
> > >  include/sbi_utils/fdt/fdt_helper.h |  2 +
> > >  lib/utils/fdt/fdt_helper.c         | 61 ++++++++++++++++++++++++++++++
> > >  platform/generic/platform.c        | 13 ++++++-
> > >  4 files changed, 90 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
> > > index 2941809e..97072c09 100644
> > > --- a/include/sbi/sbi_hart.h
> > > +++ b/include/sbi/sbi_hart.h
> > > @@ -135,6 +135,21 @@ struct sbi_hart_features {
> > >         unsigned int pmp_log2gran;
> > >         unsigned int mhpm_mask;
> > >         unsigned int mhpm_bits;
> > > +       /** True if riscv,pmwid was present in DT */
> > > +       bool has_pmwid;
> > > +       u32 pmwid;
> > > +       /**
> > > +        * Platform-defined bitmap of M-mode WIDs
> > > +        * (from DT riscv,pmwidlist). Zero means
> > > +        * absent/unrestricted.
> > > +        */
> > > +       u64 pmwidlist;
> > > +       /**
> > > +        * Platform-defined bitmap of S/U-mode WIDs
> > > +        * (from DT riscv,pmlwidlist). Zero means
> > > +        * absent/unrestricted.
> > > +        */
> > > +       u64 pmlwidlist;
> Oza: pmlwidlist defines which WIDs M-mode is permitted to assign to
> S-mode. But next-wid is never validated against it.

Yes, will add checks on DT properties.

> > >  };
> > >
> > >  extern unsigned long hart_features_offset;
> > > diff --git a/include/sbi_utils/fdt/fdt_helper.h b/include/sbi_utils/fdt/fdt_helper.h
> > > index 75a564d1..3f3d091b 100644
> > > --- a/include/sbi_utils/fdt/fdt_helper.h
> > > +++ b/include/sbi_utils/fdt/fdt_helper.h
> > > @@ -56,6 +56,8 @@ int fdt_parse_timebase_frequency(const void *fdt, unsigned long *freq);
> > >
> > >  int fdt_parse_isa_extensions_all_harts(const void *fdt);
> > >
> > > +int fdt_parse_worlds_all_harts(const void *fdt);
> > > +
> > >  int fdt_parse_gaisler_uart_node(const void *fdt, int nodeoffset,
> > >                                 struct platform_uart_data *uart);
> > >
> > > diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
> > > index ad4efaaf..8b40cd28 100644
> > > --- a/lib/utils/fdt/fdt_helper.c
> > > +++ b/lib/utils/fdt/fdt_helper.c
> > > @@ -457,6 +457,67 @@ int fdt_parse_isa_extensions_all_harts(const void *fdt)
> > >         return 0;
> > >  }
> > >
> > > +int fdt_parse_worlds_all_harts(const void *fdt)
> > > +{
> > > +       u32 hartid;
> > > +       const fdt32_t *val;
> > > +       struct sbi_scratch *scratch;
> > > +       struct sbi_hart_features *hfeatures;
> > > +       int err, cpu_offset, cpus_offset, len;
> > > +
> > > +       if (!fdt)
> > > +               return SBI_EINVAL;
> > > +
> > > +       cpus_offset = fdt_path_offset(fdt, "/cpus");
> > > +       if (cpus_offset < 0)
> > > +               return cpus_offset;
> > > +
> > > +       fdt_for_each_subnode(cpu_offset, fdt, cpus_offset) {
> > what about riscv,nworlds ? I think you should parse this and based on
> > that assume wid range - and rest of the wids should be rejected.
> > > +               err = fdt_parse_hart_id(fdt, cpu_offset, &hartid);
> > > +               if (err)
> > > +                       continue;
> > > +
> > > +               if (!fdt_node_is_enabled(fdt, cpu_offset))
> > > +                       continue;
> > > +
> > > +               scratch = sbi_hartid_to_scratch(hartid);
> > > +               if (!scratch)
> > > +                       return SBI_ENOENT;
> > > +
> > > +               hfeatures = sbi_hart_features_ptr(scratch);
> > > +               if (!hfeatures)
> > > +                       return SBI_ENOENT;
> > > +
> > > +               val = fdt_getprop(fdt, cpu_offset, "riscv,pmwid", &len);
> > > +               if (val && len == sizeof(fdt32_t)) {
> > > +                       hfeatures->pmwid = fdt32_to_cpu(*val);
> > > +                       hfeatures->has_pmwid = true;
> > > +               }
> Oza: Nothing prevents assigning the same WID to both M-mode and S-mode
> - should not be identical for both worlds.

Agreed. Will add validation in __fdt_parse_domain() to reject domains
where next-wid == pmwid.

Thanks,
Peter Lin