[PATCH v2 18/20] platform: generic: mips eyeq7h: fix NCORE registers access from clusters 1..2

[Vladimir Kondratiev]

CPU clusters 1 and 2 cannot access NCORE registers through AUX ports.
AUX ports of clusters 1 and 2 are connected to NCORE through east port.
East port has no access to NCORE registers address space.

Re-route NCORE registers range to MEM port by re-configuring MMIO
regions in the GCR. REsulting map is as below. Mind a gap between
regions [1] and [2]; this gap covering NCORE registers now routed
to the default MEM port
Cluster 0: 4 MMIO regions
  [0] : 0x0000000000000000-0x000000001fff0000 AUX0 UC|UCA
  [1] : 0x0000000020000000-0x00000000677f0000 AUX0    ANY
  [2] : 0x0000000080000000-0x0000001fffff0000 AUX0 UC|UCA
  [3] : --disabled--
Cluster 1: 4 MMIO regions
  [0] : 0x0000000000000000-0x000000001fff0000 AUX0 UC|UCA
  [1] : 0x0000000020000000-0x00000000677f0000 AUX0    ANY
  [2] : 0x0000000080000000-0x0000001fffff0000 AUX0 UC|UCA
  [3] : --disabled--
Cluster 2: 4 MMIO regions
  [0] : 0x0000000000000000-0x000000001fff0000 AUX0 UC|UCA
  [1] : 0x0000000020000000-0x00000000677f0000 AUX0    ANY
  [2] : 0x0000000080000000-0x0000001fffff0000 AUX0 UC|UCA
  [3] : --disabled--

Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev at mobileye.com>
---
 platform/generic/include/mips/p8700.h | 18 ++++++++++++++++++
 platform/generic/mips/eyeq7h.c        |  7 +++++++
 2 files changed, 25 insertions(+)

diff --git a/platform/generic/include/mips/p8700.h b/platform/generic/include/mips/p8700.h
index 0675635565589105594c231505be8b094ca4a25a..6071ddd2d0adbe02268366d1997d8d56b6b781b9 100644
--- a/platform/generic/include/mips/p8700.h
+++ b/platform/generic/include/mips/p8700.h
@@ -144,6 +144,24 @@ extern const struct p8700_cm_info *p8700_cm_info;
 #define L2SM_COP_RESULT_ABORT_OK	3
 #define L2SM_COP_RESULT_ABORT_ERROR	4
 #define GCR_L2SM_COP_PRESENT		BIT(31)
+/* MMIO regions. Actual count in GCR_GLOBAL_CONFIG.GCR_GC_NUM_MMIOS */
+#define GCR_MMIO_BOTTOM(n)		(0x700 + (n) * 0x10) // n = 0..7
+#define GCR_MMIO_TOP(n)			(0x708 + (n) * 0x10) // n = 0..7
+#define GCR_MMIO_ADDR			GENMASK(47, 16) // both top and bottom
+#define GCR_MMIO_BOTTOM_CCA		GENMASK(9, 8)
+#define GCR_MMIO_BOTTOM_FORCE_NC	BIT(6)
+/*
+ * 15:12 - reserved
+ * 11 - AUX3
+ * 10 - AUX2
+ * 9  - AUX1
+ * 8  - AUX0
+ * 7:1 - reserved
+ * 0  - Main memory port; MEM
+ */
+#define GCR_MMIO_BOTTOM_PORT		GENMASK(5, 2)
+#define GCR_MMIO_BOTTOM_DIS_RQ_LIM	BIT(1)
+#define GCR_MMIO_BOTTOM_EN		BIT(0)
 
 /* CPC Block offsets */
 #define CPC_PWRUP_CTL		0x0030
diff --git a/platform/generic/mips/eyeq7h.c b/platform/generic/mips/eyeq7h.c
index fb4cccc2bf4de4914b650e3934fa04418e594e58..9a3cccae9166c5760bc0f3d6a5fbe1b8909991d5 100644
--- a/platform/generic/mips/eyeq7h.c
+++ b/platform/generic/mips/eyeq7h.c
@@ -37,6 +37,7 @@
 #define OLB_ACC1		0x65000000
 #define OLB_XNN0		0x43600000
 #define OLB_XNN1		0x63600000
+#define NCORE			0x67800000
 #define OLB_WEST		0x48600000
 #define OLB_WEST_TSTCSR		0x60
 #define TSTCSR_PALLADIUM	BIT(0)
@@ -367,6 +368,12 @@ static int eyeq7h_nascent_init(void)
 			     (void *)(cm_base + L2_PFT_CONTROL_OFFSET));
 		__raw_writel(0x15ff,
 			     (void *)(cm_base + L2_PFT_CONTROL_B_OFFSET));
+		/*
+		 * Remove access to NCORE CSRs from mmio region 1
+		 * which is routed to AUX. NCORE to use default route through MEM.
+		 */
+		__raw_writeq(NCORE-1, (void *)(cm_base + GCR_MMIO_TOP(1)));
+		mb();
 	}
 
 	/* Per core set up */

-- 
2.43.0