[PATCH 20/22] platform: generic: mips eyeq7h: synchronize timers across clusters

[Vladimir Kondratiev]

Use eyeq7 specific method to synchronously restart architectural
mtimer and eyeq7h specific high-resolution timer with common
hardware trigger. This ensures all timers are precisely in sync

Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev at mobileye.com>
---
 platform/generic/include/mips/mips-cm.h |  1 +
 platform/generic/include/mips/p8700.h   |  5 +++++
 platform/generic/mips/eyeq7h.c          | 17 +++++++++++++++++
 3 files changed, 23 insertions(+)

diff --git a/platform/generic/include/mips/mips-cm.h b/platform/generic/include/mips/mips-cm.h
index 84f8619b4a1b..d61cf104b885 100644
--- a/platform/generic/include/mips/mips-cm.h
+++ b/platform/generic/include/mips/mips-cm.h
@@ -76,6 +76,7 @@ CPC_CX_ACCESSOR_RW(32, CPC_Cx_STAT_CONF, stat_conf)
 	CPS_ACCESSOR_RW(cpc, sz, CPC_OFFSET + (off), name)
 
 CPC_ACCESSOR_RW(32, CPC_PWRUP_CTL, pwrup_ctl)
+CPC_ACCESSOR_RW(64, CPC_TIMECTL, timectl)
 CPC_ACCESSOR_RW(64, CPC_HRTIME, hrtime)
 CPC_ACCESSOR_RW(32, CPC_CM_STAT_CONF, cm_stat_conf)
 
diff --git a/platform/generic/include/mips/p8700.h b/platform/generic/include/mips/p8700.h
index 4530fdf06fd9..067563556558 100644
--- a/platform/generic/include/mips/p8700.h
+++ b/platform/generic/include/mips/p8700.h
@@ -147,6 +147,11 @@ extern const struct p8700_cm_info *p8700_cm_info;
 
 /* CPC Block offsets */
 #define CPC_PWRUP_CTL		0x0030
+#define CPC_TIMECTL		0x0058
+#define TIMECTL_HARMED		BIT(3)
+#define TIMECTL_HSTOP		BIT(2)
+#define TIMECTL_MARMED		BIT(1)
+#define TIMECTL_MSTOP		BIT(0)
 #define CPC_HRTIME		0x0090
 #define CPC_CM_STAT_CONF	0x1008
 
diff --git a/platform/generic/mips/eyeq7h.c b/platform/generic/mips/eyeq7h.c
index b4b03bf95eb3..2d4a81d7b335 100644
--- a/platform/generic/mips/eyeq7h.c
+++ b/platform/generic/mips/eyeq7h.c
@@ -45,6 +45,9 @@
 #define TSTCSR_MIPS12_PRESENT	GENMASK(3, 2)
 #define TSTCSR_ACC_PRESENT	GENMASK(5, 4)
 
+#define OLB_WEST_CFG		0x68
+#define WEST_CFG_MIPS_MTIME_START	BIT(8)
+
 /* Use in nascent init - not have DTB yet */
 #define DRAM_ADDRESS		0x800000000UL
 #define DRAM_SIZE		0x800000000UL
@@ -295,6 +298,20 @@ static void eyeq7h_init_clusters(void)
 		eyeq7h_power_up_other_cluster(INSERT_FIELD(0, P8700_HARTID_CLUSTER, i));
 	}
 	eyeq7h_active_clusters = num_clusters;
+	/**
+	 * sync timers in all clusters. EQ7 have counters restart pins for clusters
+	 * connected to the OLB.
+	 * Stop/arm all counters, then restart all at once
+	 */
+	for (int i = 0; i < num_clusters; i++) {
+		write_cpc_timectl(INSERT_FIELD(0, P8700_HARTID_CLUSTER, i),
+				  TIMECTL_HARMED | TIMECTL_HSTOP | TIMECTL_MARMED | TIMECTL_MSTOP);
+	}
+	{
+		u32 cfg = readl((void*)OLB_WEST + OLB_WEST_CFG);
+
+		writel(cfg | WEST_CFG_MIPS_MTIME_START, (void*)OLB_WEST + OLB_WEST_CFG);
+	}
 }
 
 static int eyeq7h_early_init(bool cold_boot)
-- 
2.43.0