[PATCH v4 0/3] Add eager FP and RISC-V vector context switching support

[dave.patel at riscstar.com]

Hi Samuel, Radim,
                Thank you for taking out time and reviewing the patches,
has been some insightful comment and appreciate your inputs and feedback.

I have covered all your comments, please can you have a look and let me know.

Changes since v3:

Patch 1 :
	-- Added whole registers vs8r/vl8r instead of vse8/vle8 for save/restore.
	   So removed vse/vle to improve security.
	-- I have removed vl/vtype which only save the used registers and instead
	   using vs8r/vl8r.
	-- Init check for vlenb with SBI_MAX_VLENB
	-- Updated license information to match with other source files.
	-- decluttered all the dependencies of vector related dependencies in
	   patch 2 and 3 for eg. adding "({ ... })" is a superior macro wrapper.
Patch 2 :
	-- Vector related changes moved to patch 1.
Patch 3 :
	-- removed random artifacts and removed vector related changes to patch 1.


I have tested this across the 2 s-mode domains doing context switch and both
floating point and vector retains the values across the context.

Thanks and Regards,
Dave

Signed-off-by: Dave Patel <dave.patel at riscstar.com>