[PATCH v3 1/3] lib: sbi: Add RISC-V vector context save/restore support

[Radim Krčmář]

2026-03-31T06:58:55+01:00, <dave.patel at riscstar.com>:
> From: Dave Patel <dave.patel at riscstar.com>
>
> Eager context switch: Add support for saving and restoring RISC-V vector
> extension state in OpenSBI. This introduces a per-hart vector context
> structure and helper routines to perform full context save and restore.
>
> The vector context includes vl, vtype, vcsr CSRs along with storage for all
> 32 vector registers. The register state is saved and restored using byte-wise
> vector load/store instructions (vse8.v/vle8.v), making the implementation
> independent of current SEW/LMUL configuration.
>
> The implementation follows an eager context switching model where the entire
> vector state is saved and restored on every context switch. This provides a
> simple and deterministic mechanism without requiring lazy trap-based
> management.
>
> Notes:
> - The SBI_MAX_VLENB is configured using CONFIG_SBI_MAX_VLENB.
>
> Signed-off-by: Dave Patel <dave.patel at riscstar.com>
> ---

You missed my comment on [v2 1/3]:
https://lore.kernel.org/opensbi/DHG4IUERGFUV.3TT9CFPZ9YEDG@qti.qualcomm.com/

The two points are:
1. Possible cross-domain data access.
2. Writes to read-only CSRs.

Thanks.