[PATCH] lib: serial: sifive-uart: add shared memory region for SiFive UART

[Anup Patel]

On Thu, Aug 14, 2025 at 6:46 PM Yu-Chien Peter Lin <peter.lin at sifive.com> wrote:
>
> Add shared memory region so the driver has permission
> to access it in OpenSBI.
>
> Signed-off-by: Yu-Chien Peter Lin <peter.lin at sifive.com>

LGTM.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup


> ---
>  lib/utils/serial/sifive-uart.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/lib/utils/serial/sifive-uart.c b/lib/utils/serial/sifive-uart.c
> index 3581d47a..55637137 100644
> --- a/lib/utils/serial/sifive-uart.c
> +++ b/lib/utils/serial/sifive-uart.c
> @@ -9,6 +9,7 @@
>
>  #include <sbi/riscv_io.h>
>  #include <sbi/sbi_console.h>
> +#include <sbi/sbi_domain.h>
>  #include <sbi_utils/serial/sifive-uart.h>
>
>  /* clang-format off */
> @@ -111,5 +112,7 @@ int sifive_uart_init(unsigned long base, u32 in_freq, u32 baudrate)
>
>         sbi_console_set_device(&sifive_console);
>
> -       return 0;
> +       return sbi_domain_root_add_memrange(base, PAGE_SIZE, PAGE_SIZE,
> +                                           (SBI_DOMAIN_MEMREGION_MMIO |
> +                                           SBI_DOMAIN_MEMREGION_SHARED_SURW_MRW));
>  }
> --
> 2.48.0
>
>
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