[PATCH v5 05/10] platform: generic: mips: add a dts file
Anup Patel
anup at brainfault.org
Mon May 19 22:31:46 PDT 2025
On Tue, May 20, 2025 at 3:29 AM Chao-ying Fu <icebergfu at gmail.com> wrote:
>
> We add a dts file for 4 cores 2 threads each on a Boston board.
Even this should be part of your early boot stage before OpenSBI.
Regards,
Anup
>
> Signed-off-by: Chao-ying Fu <cfu at mips.com>
> ---
> platform/generic/mips/mips,boston-p8700.dts | 347 ++++++++++++++++++++
> 1 file changed, 347 insertions(+)
> create mode 100644 platform/generic/mips/mips,boston-p8700.dts
>
> diff --git a/platform/generic/mips/mips,boston-p8700.dts b/platform/generic/mips/mips,boston-p8700.dts
> new file mode 100644
> index 0000000..6da646c
> --- /dev/null
> +++ b/platform/generic/mips/mips,boston-p8700.dts
> @@ -0,0 +1,347 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (c) 2025 MIPS
> + *
> + */
> +
> +/dts-v1/;
> +
> +#define CM_BASE 0x16100000
> +#define APLIC_M_BASE (CM_BASE + 0x40000)
> +#define APLIC_S_BASE (CM_BASE + 0x60000)
> +#define MSWI_BASE (CM_BASE + 0x50000)
> +#define MTIMER_BASE (MSWI_BASE + 0x4000)
> +#define CPC_TIMER (CM_BASE + 0x8050)
> +
> +#define IRQ_TYPE_LEVEL_HIGH 4
> +#define UART_INT 4
> +#define PCIE2_INT 7
> +
> +#define BITFILE_FREQUENCY 25000000
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + model = "MIPS P8700";
> + compatible = "mips,p8700";
> +
> + chosen {
> + stdout-path = &uart0;
> + // For Qemu
> + //bootargs = "root=/dev/sda rw earlycon console=ttyS0,115200n8r";
> + // For a Boston board
> + bootargs = "root=/dev/mmcblk0p5 rw rootwait earlycon console=ttyS0,115200n8r";
> +
> + opensbi-domains {
> + compatible = "opensbi,domain,config";
> +
> + tmem: tmem {
> + compatible = "opensbi,domain,memregion";
> + base = <0x0 0x80000000>;
> + order = <31>;
> + };
> +
> + allmem: allmem {
> + compatible = "opensbi,domain,memregion";
> + base = <0x0 0x0>;
> + order = <64>;
> + };
> +
> + tdomain: trusted-domain {
> + compatible = "opensbi,domain,instance";
> + possible-harts = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5 &cpu6 &cpu7>;
> + regions = <&tmem 0x3f>, <&allmem 0x3f>;
> + };
> + };
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <BITFILE_FREQUENCY>;
> +
> + cpu0: cpu at 0 {
> + device_type = "cpu";
> + compatible = "riscv";
> + riscv,cbom-block-size = <64>;
> + opensbi-domain = <&tdomain>;
> + mmu-type = "riscv,sv39";
> + riscv,isa = "rv64imafdcsu";
> + status = "okay";
> + reg = <0x00000000>;
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu1: cpu at 1 {
> + device_type = "cpu";
> + compatible = "riscv";
> + riscv,cbom-block-size = <64>;
> + opensbi-domain = <&tdomain>;
> + mmu-type = "riscv,sv39";
> + riscv,isa = "rv64imafdcsu";
> + status = "okay";
> + reg = <0x00000001>;
> +
> + cpu1_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu2: cpu at 2 {
> + device_type = "cpu";
> + compatible = "riscv";
> + riscv,cbom-block-size = <64>;
> + opensbi-domain = <&tdomain>;
> + mmu-type = "riscv,sv39";
> + riscv,isa = "rv64imafdcsu";
> + status = "okay";
> + reg = <0x00000010>;
> +
> + cpu2_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu3: cpu at 3 {
> + device_type = "cpu";
> + compatible = "riscv";
> + riscv,cbom-block-size = <64>;
> + opensbi-domain = <&tdomain>;
> + mmu-type = "riscv,sv39";
> + riscv,isa = "rv64imafdcsu";
> + status = "okay";
> + reg = <0x00000011>;
> +
> + cpu3_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu4: cpu at 4 {
> + device_type = "cpu";
> + compatible = "riscv";
> + riscv,cbom-block-size = <64>;
> + opensbi-domain = <&tdomain>;
> + mmu-type = "riscv,sv39";
> + riscv,isa = "rv64imafdcsu";
> + status = "okay";
> + reg = <0x00000020>;
> +
> + cpu4_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu5: cpu at 5 {
> + device_type = "cpu";
> + compatible = "riscv";
> + riscv,cbom-block-size = <64>;
> + opensbi-domain = <&tdomain>;
> + mmu-type = "riscv,sv39";
> + riscv,isa = "rv64imafdcsu";
> + status = "okay";
> + reg = <0x00000021>;
> +
> + cpu5_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu6: cpu at 6 {
> + device_type = "cpu";
> + compatible = "riscv";
> + riscv,cbom-block-size = <64>;
> + opensbi-domain = <&tdomain>;
> + mmu-type = "riscv,sv39";
> + riscv,isa = "rv64imafdcsu";
> + status = "okay";
> + reg = <0x00000030>;
> +
> + cpu6_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu7: cpu at 7 {
> + device_type = "cpu";
> + compatible = "riscv";
> + riscv,cbom-block-size = <64>;
> + opensbi-domain = <&tdomain>;
> + mmu-type = "riscv,sv39";
> + riscv,isa = "rv64imafdcsu";
> + status = "okay";
> + reg = <0x00000031>;
> +
> + cpu7_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> + };
> +
> + memory at 80000000 {
> + device_type = "memory";
> + reg = <0x80000000 0x80000000>;
> + };
> +
> + pci2: pci at 14000000 {
> + compatible = "xlnx,axi-pcie-host-1.00.a";
> + device_type = "pci";
> + reg = <0x14000000 0x2000000>;
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> +
> + interrupt-parent = <&aplic_s0>;
> + interrupts = <PCIE2_INT IRQ_TYPE_LEVEL_HIGH>;
> +
> + ranges = <0x02000000 0 0x16000000
> + 0x16000000 0 0x100000>;
> +
> + bus-range = <0x00 0xff>;
> +
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &pci2_intc 1>,
> + <0 0 0 2 &pci2_intc 2>,
> + <0 0 0 3 &pci2_intc 3>,
> + <0 0 0 4 &pci2_intc 4>;
> +
> + pci2_intc: interrupt-controller {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + };
> +
> + pci2_root at 0,0 {
> + compatible = "pci10ee,7021", "pci-bridge";
> + reg = <0x00000000 0 0 0 0>;
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> +
> + eg20t_bridge at 1,0,0 {
> + compatible = "pci8086,8800", "pci-bridge";
> + reg = <0x00010000 0 0 0 0>;
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> +
> + eg20t_mac at 2,0,1 {
> + compatible = "pci8086,8802", "intel,pch-gbe";
> + reg = <0x00020100 0 0 0 0>;
> + phy-reset-gpios = <&eg20t_gpio 6 1>;
> + };
> +
> + eg20t_gpio: eg20t_gpio at 2,0,2 {
> + compatible = "pci8086,8803", "intel,eg20t-gpio";
> + reg = <0x00020200 0 0 0 0>;
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + eg20t_i2c at 2,12,2 {
> + compatible = "pci8086,8817";
> + reg = <0x00026200 0 0 0 0>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + rtc at 68 {
> + compatible = "st,m41t81s";
> + reg = <0x68>;
> + };
> + };
> + };
> + };
> + };
> +
> + uart0: uart at 17ffe000 {
> + compatible = "ns16550a";
> + reg = <0x17ffe000 0x1000>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> +
> + interrupt-parent = <&aplic_s0>;
> + interrupts = <UART_INT IRQ_TYPE_LEVEL_HIGH>;
> +
> + clock-frequency = <BITFILE_FREQUENCY>;
> +
> + u-boot,dm-pre-reloc;
> + };
> +
> + lcd: lcd at 17fff000 {
> + compatible = "img,boston-lcd";
> + reg = <0x17fff000 0x8>;
> + };
> +
> + flash at 18000000 {
> + compatible = "cfi-flash";
> + reg = <0x18000000 0x8000000>;
> + bank-width = <2>;
> + };
> +
> + soc {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "simple-bus";
> + ranges;
> +
> + aplic_s0: interrupt-controller at 16160000 {
> + #interrupt-cells = <0x00000002>;
> + compatible = "riscv,aplic";
> + interrupt-controller;
> + interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>, <&cpu2_intc 9>, <&cpu3_intc 9>, <&cpu4_intc 9>, <&cpu5_intc 9>, <&cpu6_intc 9>, <&cpu7_intc 9>;
> + reg = <APLIC_S_BASE 0x00008000>;
> + riscv,num-sources = <0x00000035>;
> + };
> +
> + aplic_m0: interrupt-controller at 16140000 {
> + #interrupt-cells = <0x00000002>;
> + riscv,delegate = <&aplic_s0 0x00000001 0x00000035>;
> + riscv,children = <&aplic_s0>;
> + compatible = "riscv,aplic";
> + interrupt-controller;
> + interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>, <&cpu2_intc 11>, <&cpu3_intc 11>, <&cpu4_intc 11>, <&cpu5_intc 11>, <&cpu6_intc 11>, <&cpu7_intc 11>;
> + reg = <APLIC_M_BASE 0x00008000>;
> + riscv,num-sources = <0x00000035>;
> + };
> +
> + mswi0: interrupt-controller at 16150000 {
> + compatible = "riscv,aclint-mswi";
> + interrupts-extended = <&cpu0_intc 3>, <&cpu1_intc 3>, <&cpu2_intc 3>, <&cpu3_intc 3>, <&cpu4_intc 3>, <&cpu5_intc 3>, <&cpu6_intc 3>, <&cpu7_intc 3>;
> + reg = <MSWI_BASE 0x4000>;
> + interrupt-controller;
> + #interrupt-cells = <0>;
> + };
> +
> + mtimer0: timer at 16154000 {
> + compatible = "riscv,aclint-mtimer";
> + reg = <CPC_TIMER 0x8>,
> + <MTIMER_BASE 0x7ff8>;
> + interrupts-extended = <&cpu0_intc 7>, <&cpu1_intc 7>, <&cpu2_intc 7>, <&cpu3_intc 7>, <&cpu4_intc 7>, <&cpu5_intc 7>, <&cpu6_intc 7>, <&cpu7_intc 7>;
> + };
> + };
> +};
> --
> 2.47.1
>
>
> --
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