[PATCH v2 7/9] lib/utils: Fix Zicntr detection in fdt_cpu_fixup

[Xiang W]

As a result of the change in the boot sequence, it is now
possible to check in fdt_cpu_fixup if a specific HART supports
CY/IR, instead of assuming that all HARTs have the same support
for CY/IR.

Signed-off-by: Xiang W <wxjstz at 126.com>
---
 lib/utils/fdt/fdt_fixup.c | 24 ++++++++++++++----------
 1 file changed, 14 insertions(+), 10 deletions(-)

diff --git a/lib/utils/fdt/fdt_fixup.c b/lib/utils/fdt/fdt_fixup.c
index f3fe8af9..ed9b77c1 100644
--- a/lib/utils/fdt/fdt_fixup.c
+++ b/lib/utils/fdt/fdt_fixup.c
@@ -108,22 +108,13 @@ int fdt_add_cpu_idle_states(void *fdt, const struct sbi_cpu_idle_state *state)
 
 void fdt_cpu_fixup(void *fdt)
 {
-	struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
+	struct sbi_scratch *rscratch;
 	struct sbi_domain *dom = sbi_domain_thishart_ptr();
 	int err, cpu_offset, cpus_offset, len;
 	const char *mmu_type, *extensions;
 	u32 hartid, hartindex;
 	bool emulated_zicntr;
 
-	/*
-	 * Claim Zicntr extension in riscv,isa-extensions if
-	 *  1. OpenSBI can emulate time CSR with a timer
-	 *  2. The other two CSRs specified by Zicntr are available
-	 */
-	emulated_zicntr = sbi_timer_get_device() != NULL &&
-			  sbi_hart_has_csr(scratch, SBI_HART_CSR_CYCLE) &&
-			  sbi_hart_has_csr(scratch, SBI_HART_CSR_INSTRET);
-
 	err = fdt_open_into(fdt, fdt, fdt_totalsize(fdt) + 32);
 	if (err < 0)
 		return;
@@ -153,6 +144,19 @@ void fdt_cpu_fixup(void *fdt)
 			fdt_setprop_string(fdt, cpu_offset, "status",
 					   "disabled");
 
+		rscratch = sbi_hartindex_to_scratch(hartindex);
+		if (!rscratch)
+			continue;
+
+		/*
+		 * Claim Zicntr extension in riscv,isa-extensions if
+		 *  1. OpenSBI can emulate time CSR with a timer
+		 *  2. The other two CSRs specified by Zicntr are available
+		 */
+		emulated_zicntr =
+			sbi_timer_get_device() != NULL &&
+			sbi_hart_has_csr(rscratch, SBI_HART_CSR_CYCLE) &&
+			sbi_hart_has_csr(rscratch, SBI_HART_CSR_INSTRET);
 		if (!emulated_zicntr)
 			continue;
 
-- 
2.47.2