[PATCH v1] generic: mips: support harts to boot from mips_warm_boot

[Chao-ying Fu]

On Wed, Jul 16, 2025 at 5:04 PM Samuel Holland
<samuel.holland at sifive.com> wrote:
>
> On 2025-07-10 6:17 PM, Chao-ying Fu wrote:
> > We program reset base for harts (other than hart 0) to boot at
> > mips_warm_boot that jumps to _start_warm. This helps to skip some code
> > sequence to speed up.
> >
> > Signed-off-by: Chao-ying Fu <cfu at mips.com>
> > ---
> >  platform/generic/mips/p8700.c | 19 +++++++++++++++++++
> >  1 file changed, 19 insertions(+)
> >
> > diff --git a/platform/generic/mips/p8700.c b/platform/generic/mips/p8700.c
> > index 888a45c..687912a 100644
> > --- a/platform/generic/mips/p8700.c
> > +++ b/platform/generic/mips/p8700.c
> > @@ -140,6 +140,22 @@ static void power_up_other_cluster(u32 hartid)
> >  }
> >  #endif
> >
> > +static void __attribute__((naked,no_instrument_function,aligned(4096)))
> > +mips_warm_boot(void)
> > +{
> > +  __asm__ __volatile__(
> > +     "       j       1f\n"
> > +     "       .align  2\n"
> > +     "       j       1f\n"
> > +     "       .align  2\n"
> > +     "       j       1f\n"
> > +     "       .align  2\n"
> > +     "       j       1f\n"
> > +     "1:     lla     t0, _start_warm\n"
> > +     "       jr      t0\n"
>
> The double/indirect jump is not necessary. jal (j) range is +/- 1 MiB, which is
> much larger than the OpenSBI firmware size. So each entry point can jump to
> _start_warm directly.
>
> Regards,
> Samuel
  Yes, we can use only one jump instruction to _start_warm for each
entry point, as you pointed out.
I will send out a new patch.

  Thanks a lot!

Regards,
Chao-ying

>
> > +     );
> > +}
> > +
> >  static int mips_hart_start(u32 hartid, ulong saddr)
> >  {
> >       unsigned int stat;
> > @@ -150,6 +166,9 @@ static int mips_hart_start(u32 hartid, ulong saddr)
> >       if (hartid == 0)
> >               return SBI_ENOTSUPP;
> >
> > +     /* Change reset base to mips_warm_boot */
> > +     write_gcr_co_reset_base(hartid, (unsigned long)mips_warm_boot, local_p);
> > +
> >       if (cpu_hart(hartid) == 0) {
> >               /* Ensure its coherency is disabled */
> >               write_gcr_co_coherence(hartid, 0, local_p);
>