[PATCH 2/3] firmware: Replace sole uses of REGBYTES with __SIZEOF_LONG__
Anup Patel
anup at brainfault.org
Tue Jul 22 03:46:22 PDT 2025
On Thu, Jul 10, 2025 at 4:59 AM Jessica Clarke <jrtc27 at jrtc27.com> wrote:
>
> This code has nothing to do with the ISA's registers, it's about the
> format of ELF relocations. As such, __SIZEOF_LONG__, being a language /
> ABI-level property, is a more appropriate constant to use. This also
> makes it easier to support CHERI, where general-purpose registers are
> extended to be capabilities, not just integers, and so the register size
> is not the same as the machine word size. This also happens to make it
> more correct for RV64ILP32, where the registers are 64-bit integers but
> the ABI is 32-bit (both for long and for the ELF format), though
> properly supporting that ABI is not part of the motivation here, just a
> consequence of improving the code for CHERI.
>
> Signed-off-by: Jessica Clarke <jrtc27 at jrtc27.com>
LGTM.
Reviewed-by: Anup Patel <anup at brainfault.org>
Applied this patch to the riscv/opensbi repo.
Thanks,
Anup
> ---
> firmware/fw_base.S | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/firmware/fw_base.S b/firmware/fw_base.S
> index 2498797..aa8e264 100644
> --- a/firmware/fw_base.S
> +++ b/firmware/fw_base.S
> @@ -80,17 +80,17 @@ _sc_fail:
> lla t1, __rel_dyn_end
> beq t0, t1, _relocate_done
> 2:
> - REG_L t5, REGBYTES(t0) /* t5 <-- relocation info:type */
> + REG_L t5, __SIZEOF_LONG__(t0) /* t5 <-- relocation info:type */
> li t3, R_RISCV_RELATIVE /* reloc type R_RISCV_RELATIVE */
> bne t5, t3, 3f
> REG_L t3, 0(t0)
> - REG_L t5, (REGBYTES * 2)(t0) /* t5 <-- addend */
> + REG_L t5, (__SIZEOF_LONG__ * 2)(t0) /* t5 <-- addend */
> add t5, t5, t2
> add t3, t3, t2
> REG_S t5, 0(t3) /* store runtime address to the GOT entry */
>
> 3:
> - addi t0, t0, (REGBYTES * 3)
> + addi t0, t0, (__SIZEOF_LONG__ * 3)
> blt t0, t1, 2b
> _relocate_done:
> /* At this point we are running from link address */
> --
> 2.34.1
>
>
> --
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