[PATCH v3 1/2] lib: sbi: Remove redundant call to sbi_hart_expected_trap_addr()

[Anup Patel]

On Thu, Jul 3, 2025 at 8:50 PM Alvin Chang <alvinga at andestech.com> wrote:
>
> The variable "sbi_hart_expected_trap" has already been extern variable.
> Therefore, the program can directly refer to it instead of calling
> sbi_hart_expected_trap_addr().
>
> Signed-off-by: Alvin Chang <alvinga at andestech.com>

LGTM.

Reviewed-by: Anup Patel <anup at brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  include/sbi/sbi_csr_detect.h | 4 ++--
>  include/sbi/sbi_hart.h       | 4 ----
>  lib/sbi/sbi_illegal_atomic.c | 4 ++--
>  lib/sbi/sbi_unpriv.c         | 6 +++---
>  4 files changed, 7 insertions(+), 11 deletions(-)
>
> diff --git a/include/sbi/sbi_csr_detect.h b/include/sbi/sbi_csr_detect.h
> index 89ba294..097c31c 100644
> --- a/include/sbi/sbi_csr_detect.h
> +++ b/include/sbi/sbi_csr_detect.h
> @@ -18,7 +18,7 @@
>         ({                                                              \
>         register ulong tinfo asm("a3") = (ulong)trap;                   \
>         register ulong ttmp asm("a4");                                  \
> -       register ulong mtvec = sbi_hart_expected_trap_addr();           \
> +       register ulong mtvec = (ulong)sbi_hart_expected_trap;           \
>         register ulong ret = 0;                                         \
>         ((struct sbi_trap_info *)(trap))->cause = 0;                    \
>         asm volatile(                                                   \
> @@ -37,7 +37,7 @@
>         ({                                                              \
>         register ulong tinfo asm("a3") = (ulong)trap;                   \
>         register ulong ttmp asm("a4");                                  \
> -       register ulong mtvec = sbi_hart_expected_trap_addr();           \
> +       register ulong mtvec = (ulong)sbi_hart_expected_trap;           \
>         ((struct sbi_trap_info *)(trap))->cause = 0;                    \
>         asm volatile(                                                   \
>                 "add %[ttmp], %[tinfo], zero\n"                         \
> diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
> index dfbe8e4..82b19dc 100644
> --- a/include/sbi/sbi_hart.h
> +++ b/include/sbi/sbi_hart.h
> @@ -134,10 +134,6 @@ int sbi_hart_reinit(struct sbi_scratch *scratch);
>  int sbi_hart_init(struct sbi_scratch *scratch, bool cold_boot);
>
>  extern void (*sbi_hart_expected_trap)(void);
> -static inline ulong sbi_hart_expected_trap_addr(void)
> -{
> -       return (ulong)sbi_hart_expected_trap;
> -}
>
>  unsigned int sbi_hart_mhpm_mask(struct sbi_scratch *scratch);
>  void sbi_hart_delegation_dump(struct sbi_scratch *scratch,
> diff --git a/lib/sbi/sbi_illegal_atomic.c b/lib/sbi/sbi_illegal_atomic.c
> index 2161b23..8fd6c55 100644
> --- a/lib/sbi/sbi_illegal_atomic.c
> +++ b/lib/sbi/sbi_illegal_atomic.c
> @@ -30,7 +30,7 @@ int sbi_illegal_atomic(ulong insn, struct sbi_trap_regs *regs)
>         {                                                                       \
>                 register ulong tinfo asm("a3");                                 \
>                 register ulong mstatus = 0;                                     \
> -               register ulong mtvec = sbi_hart_expected_trap_addr();           \
> +               register ulong mtvec = (ulong)sbi_hart_expected_trap;           \
>                 type ret = 0;                                                   \
>                 trap->cause = 0;                                                \
>                 asm volatile(                                                   \
> @@ -57,7 +57,7 @@ int sbi_illegal_atomic(ulong insn, struct sbi_trap_regs *regs)
>         {                                                                       \
>                 register ulong tinfo asm("a3");                                 \
>                 register ulong mstatus = 0;                                     \
> -               register ulong mtvec = sbi_hart_expected_trap_addr();           \
> +               register ulong mtvec = (ulong)sbi_hart_expected_trap;           \
>                 type ret = 0;                                                   \
>                 trap->cause = 0;                                                \
>                 asm volatile(                                                   \
> diff --git a/lib/sbi/sbi_unpriv.c b/lib/sbi/sbi_unpriv.c
> index 2a55d9d..f9bbec5 100644
> --- a/lib/sbi/sbi_unpriv.c
> +++ b/lib/sbi/sbi_unpriv.c
> @@ -24,7 +24,7 @@
>         {                                                                     \
>                 register ulong tinfo asm("a3");                               \
>                 register ulong mstatus = 0;                                   \
> -               register ulong mtvec = sbi_hart_expected_trap_addr();         \
> +               register ulong mtvec = (ulong)sbi_hart_expected_trap;         \
>                 type ret = 0;                                                 \
>                 trap->cause = 0;                                              \
>                 asm volatile(                                                 \
> @@ -51,7 +51,7 @@
>         {                                                                     \
>                 register ulong tinfo asm("a3") = (ulong)trap;                 \
>                 register ulong mstatus = 0;                                   \
> -               register ulong mtvec = sbi_hart_expected_trap_addr();         \
> +               register ulong mtvec = (ulong)sbi_hart_expected_trap;         \
>                 trap->cause = 0;                                              \
>                 asm volatile(                                                 \
>                         "add %[tinfo], %[taddr], zero\n"                      \
> @@ -121,7 +121,7 @@ ulong sbi_get_insn(ulong mepc, struct sbi_trap_info *trap)
>         register ulong tinfo asm("a3");
>         register ulong ttmp asm("a4");
>         register ulong mstatus = 0;
> -       register ulong mtvec = sbi_hart_expected_trap_addr();
> +       register ulong mtvec = (ulong)sbi_hart_expected_trap;
>         ulong insn = 0;
>
>         trap->cause = 0;
> --
> 2.43.0
>